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REC-CTL Duty Data Register 4 (RCDR4)
Bit :
15
Initial value :
R/W :
RCDR4 is a 12-bit write-only register that sets the timing of falling edge of the 0 pulse (short) of
REC-CTL in record or rewrite mode. In detection mode, it is used to detect the long/short pulse.
Only a word access is valid. If a byte access is attempted, correct operation is not guaranteed. If a
read is attempted, an undetermined value is read out. Bits 15 to 12 are reserved, and no write in
them is valid.
It is initialized to H'F000 by a reset, stand-by or module stop.
In record mode, set a value with the 57.5 percent duty cycle obtained from the set time T4
corresponding to the frequency φs according to the following equation. See figure 26.60, REC-
CTL Signal Generation Timing.
RCDR4 = T4 × φ s/64
φ is the servo clock frequency (= f
At bit pattern detection, set the 0 pulse long/short threshold value at REV. See figure 26.56, Duty
Discriminator.
RCDR4 = H'FFF − (T4' × φ s/80)
φs is the servo clock frequency (= f
REV (s).
14
13
12
11
—
—
—
—
CMT4B
1
1
1
1
0
—
—
—
—
W
/2) in Hz, and T4 is the set timing (s).
OSC
/2) in Hz, and T4' is the 0 pulse long/short threshold value at
OSC
10
9
8
7
CMT4A
CMT49
CMT48
CMT47
CMT46
0
0
0
0
W
W
W
W
6
5
4
3
2
CMT45
CMT44
CMT43
CMT42
0
0
0
0
0
W
W
W
W
W
Rev. 1.0, 02/00, page 695 of 1141
1
0
CMT41
CMT40
0
0
W
W
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