Vertical Sync Signal Threshold Register (Vvthr) - Hitachi H8S/2199 Hardware Manual

Single-chip microcomputer
Table of Contents

Advertisement

Csync
HVTH
Digital H separation
counter
SEPH
HC
H complement and
mask counter
HHK
OSCH
When Complementary Pulses Inserted Three Successive Times While HHKON = 1
27.2.5

Vertical Sync Signal Threshold Register (VVTHR)

Bit :
VVTH7
Initial value :
R/W :
W
The VVTHR is an 8-bit write-only register for specifying the threshold value for the digital V
separation counter; this value is used to generate the SEPV signal from the Csync signal. The
SEPV signal is set to 1 when the digital V separation counter value matches the VVTHR value
while the Csync is high, and reset to 0 when the digital V separation counter value becomes 00
while the Csync is low. Set the VVTHR value so that the SEPV signal goes high 1/2H or more
after the Vsync start point. When reset, the VVTHR is initialized to H'E0.
Figure 27.8 shows the VVTHR value and the SEPV signal generation timing.
Csync
VVTH
Digital V separation
counter
SEPV
Figure 27.8 VVTHR Value and SEPV Generation Timing
Forcible HHK
operation
Comple-
Comple-
Comple-
ment
ment
ment
Figure 27.7 Timing of HHK Operation
7
6
VVTH6
VVTH5
0
0
W
5
4
VVTH4
VVTH3
0
0
W
W
1/2 H or more
H
Forcible HHK
operation
Comple-
Comple-
Comple-
ment
ment
ment
3
2
VVTH2
VVTH1
0
0
W
W
Rev. 1.0, 02/00, page 773 of 1141
1
0
VVTH0
0
0
W
W

Advertisement

Table of Contents
loading

Table of Contents