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Bit 0 Output Switching Bit Between VideoFF and NarrowFF (VFF/NFF): Switches the
signal output from the VideoFF pin.
Bit 0
VFF/NFF
Description
0
VideoFF output
1
NarrowFF output
HSW Loop Stage Number Setting Register (HSLP)
Bit :
Initial value :
R/W :
HSLP is an 8-bit read/write register that sets the number of the loop stages when the HSW timing
generator is in loop mode. It is valid when bit 5 (LOP) of HSM2 is 1. Bits 7 to 4 set the number
of FIFO2 stages. Bits 3 to 0 set the number of FIFO1 stages.
It is not initialized by a reset or in stand-by or module stop mode; accordingly be sure to set the
number of the stages when the loop mode is used.
7
6
LOB3
LOB2
LOB1
*
*
R/W
R/W
5
4
LOB0
LOA3
*
*
R/W
R/W
R/W
3
2
1
LOA2
LOA1
*
*
*
R/W
R/W
Rev. 1.0, 02/00, page 597 of 1141
(Initial value)
0
LOA0
*
R/W
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