Hitachi H8S/2199 Hardware Manual page 1031

Single-chip microcomputer
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H'D0BA: Servo Interrupt Request Register 1 SIRQR1: Servo Interrupt
Bit
:
7
IRRDRM3
IRRDRM2 IRRDRM1
Initial value
:
0
R/W
:
R/(W)*
Drum speed error detector (lock detection) interrupt request bit
0 Drum speed error detector (lock detection) interrupt request is not generated (Initial value)
1 Drum speed error detector (lock detection) interrupt request is generated
Drum phase error detector interrupt request bit
0 Drum phase error detector interrupt request is not generated (Initial value)
1 Drum phase error detector interrupt request is generated
Note: * Only 0 can be written to clear the flag.
6
5
4
IRRCAP3 IRRCAP2 IRRCAP1 IRRHSW2 IRRHSW1
0
0
0
R/(W)*
R/(W)*
R/(W)*
Capstan phase error detector interrupt request bit
0 Capstan phase error detector interrupt request is not generated (Initial value)
1 Capstan phase error detector interrupt request is generated
Drum speed error detector (OVF, latch) interrupt request bit
0 Drum speed error detector (OVF, latch) interrupt request is not generated (Initial value)
1 Drum speed error detector (OVF, latch) interrupt request is generated
3
2
0
0
R/(W)*
R/(W)*
HSW timing generator (counter clear, capture)
interrupt request bit
0 HSW timing generator (counter clear, capture) interrupt
request is not generated
0 HSW timing generator (counter clear, capture) interrupt
request is generated
Capstan speed error detector (OVF, latch) interrupt request bit
0 Capstan speed error detector (OVF, latch) interrupt request in not generated
1 Capstan speed error detector (OVF, latch) interrupt request is generated
Capstan speed error detector (lock detection) intrerrupt request bit
0 Capstan speed error detector (lock detection) interrupt request is not generated
1 Capstan speed error detector (lock detection) interrupt request is generated
1
0
0
0
R/(W)*
R/(W)*
HSW timing generator (OVW, match, STRIG)
interrupt request bit
0 HSW timing generator (OVM, match, STRIG)
interrupt request is not generated
1 HSW timing generator (OVM, match, STRIG)
interrupt request is generated
Rev. 1.0, 02/00, page 1029 of 1141
(Initial value)
(Initial value)
(Initial value)
(Initial value)

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