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23.3.3
Master Receive Operation
In master receive mode, the master device outputs the receive clock, receives data, and returns an
acknowledge signal. The slave device transmits the data. The receive procedure and operations in
master receive mode are described below.
1. Clear TRS to 0 in ICCR to switch from transmit mode to receive mode.
2. Read ICDR to start receiving (dummy data read). When ICDR is read, a receive clock is
output in synchronization with the internal clock, and data is received.
At the ninth clock pulse the master device drives SDA low to acknowledge the data.
3. When one frame of data has been received, the IRIC flag is set to 1 in ICCR at the rise of the
ninth receive clock pulse. If IEIC is set to 1 in ICCR, a CPU interrupt is requested. If the
RDRF internal flag is 0 at this time, it is set to 1, and continuous reception is performed. If
reception of the next frame is completed before the ICDR read and IRIC flag clearing in step 4,
SCL is automatically brought to the low level in synchronization with the internal clock and
held low.
4. Read ICDR and clear IRIC to 0 in ICCR. At this time, RDRF flag is cleared to 0.
Steps 3 and 4 can be repeated to receive data continuously. At the time the mode is first switched
from master transmit mode to master receive mode and reception has just started, RDRF internal
flag is cleared to 0, therefore data reception of the next frame is automatically started. To stop
receiving, TRS bit must be set to 1 before startup of the next frame receive clock.
To stop receiving, set TRS to 1, read ICDR, then write 0 in BBSY and 0 in SCP in ICCR. This
generates a stop condition by causing a low-to-high transition of SDA while SCL is high.
Rev. 1.0, 02/00, page 494 of 1141
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