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H'D06A to H'D06B: FIFO Timing Pattern Register 2 FTPRB: HSW Timing Generator
15
Bit
:
FTPRB15
Initial value
:
*
R/W
:
W
15
Bit
:
FTPRB15
Initial value
:
*
R/W
:
W
H'D06C: DFG Reference Register 1 DFCRA: HSW Timing Generator
Bit
:
ISEL2
Initial value
:
R/W
:
Interrupt select bit
0 Interrupt request is generated by clear signal of 16-bit timer counter
1 Interrupt request is generated by VD signal in PB mode
Note: DFCRA and DFCTR are assigned to the same address.
14
13
FTPRB14
FTPRB13
*
W
W
14
13
FTPRB14
FTPRB13
*
W
W
7
6
CCLR
CKSL
0
0
W
W
16-bit counter clock source select bit
φs/4
0
φs/8
1
DFG counter clear bit
0 Normal operation
1 5-bit DFG counter is cleared
12
11
FTPRB12
FTPRB11
*
*
W
12
11
FTPRB12
FTPRB11
*
*
W
5
4
DFCRA4 DFCRA3 DFCRA2 DFCRA1
0
*
W
W
(Initial value)
(Initial value)
10
FTPRB10
FTPRB9
*
*
W
W
10
FTPRB10
FTPRB9
*
*
W
W
3
2
*
*
W
W
FIFO1 output timing setting
bits (DFCRA4 to DFCRA0)
These bits determine the
start point of FIFO1 timing.
(Initial value)
Rev. 1.0, 02/00, page 1007 of 1141
9
8
FTPRB8
*
*
W
W
9
8
FTPRB8
*
*
W
W
1
0
DFCRA0
*
*
W
W
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