Table of Contents
Advertisement
26.2.4
Register Configuration
Table 26.3 shows the register configuration of the servo port section.
Table 26.3 Register Configuration
Name
Servo port mode register
Servo monitor control register
CTL gain control register
26.2.5
Register Description
Servo Port Mode Register (SPMR)
Bit :
CTLSTOP
Initial value :
R/W
R/W :
SPMR is an 8-bit read/write register that switches the CFG input system.
It is initialized to H'5F by a reset or in stand-by mode.
Bit 7 CTLSTOP Bit (CTLSTOP) : Controls whether the CTL circuit is operated or stopped.
Bit 7
CTLSTOP
0
1
Bit 6 Reserved: Cannot be modified and is always read as 1.
Bit 5 CFG Input System Switching Bit (CFGCOMP) : Selects whether the CFG input signal
system is set to the zero cross type comparator system or digital signal input system.
Bit 5
CFGCOMP
0
1
Bits 4 to 0 Reserved: Cannot be modified and are always read as 1.
Abbrev.
SPMR
SVMCR
CTLGR
7
6
CFGCOMP
0
1
R/W
Description
CTL circuit operates
CTL circuit stops operation
Description
CFG signal input system is set to the zero cross type comparator system.
CFG signal input system is set to the digital signal input system.
R/W
Size
R/W
Byte
R/W
Byte
R/W
Byte
5
4
0
1
Initial Value
H'5F
H'C0
H'C0
3
2
1
1
Rev. 1.0, 02/00, page 561 of 1141
Address
H'D0A0
H'D0A3
H'D0A4
1
0
1
1
(Initial value)
(Initial value)
Advertisement
Table of Contents
