Hitachi H8S/2199 Hardware Manual page 421

Single-chip microcomputer
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Bit 3    Parity Error (PER): Indicates that a parity error occurred during reception using parity
addition in asynchronous mode, causing abnormal termination.
Bit 4
PER
Description
0
[Clearing conditions]
When 0 is written in PER after reading PER = 1
1
[Setting conditions]
When, in reception, the number of 1 bits in the receive data plus the parity bit does
not match the parity setting (even or odd) specified by the O/( bit in SMR1
Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCR1 is
cleared to 0.
2. If a parity error occurs, the receive data is transferred to RDR1 but the RDRF flag is not
set. Also, subsequent serial reception cannot be continued while the PER flag is set to
1. In synchronous mode, serial transmission cannot be continued, either.
Bit 2    Transmit End (TEND): Indicates that there is no valid data in TDR when the last bit of
the transmit character is sent, and transmission has been ended.
The TEND flag is read-only and cannot be modified.
Bit 2
TEND
Description
0
[Clearing conditions]
When 0 is written in TDRE after reading TDRE = 1
1
[Setting conditions]
1. When the TE bit in SCR1 is 0
2. When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character
Bit 1    Multiprocessor Bit (MPB): When reception is performed using a multiprocessor format
in asynchronous mode, MPB stores the multiprocessor bit in the receive data.
MPB is a read-only bit, and cannot be modified.
Bit 1
MPB
Description
0
[Clearing conditions]
When data with a 0 multiprocessor bit is received
1
[Setting conditions]
When data with a 1 multiprocessor bit is received
Note:
*
Retains its previous state when the RE bit in SCR1 is cleared to 0 with multiprocessor
format.
Rev. 1.0, 02/00, page 412 of 1141
*1
(Initial value)
*2
(Initial value)
(Initial value)*

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