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H'D14C: Serial Status Register SSR1: SCI1
Bit
Initial value :
R/W
Transmit data register empty
0
1
Note: * Only 0 can be written to clear the flag.
Rev. 1.0, 02/00, page 1064 of 1141
7
6
:
TDRE
RDRF
ORER
1
0
R/(W)*
R/(W)*
R/(W)*
:
Parity error
0
1
Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCR1 is cleared to 0.
2. If a parity error occurs, the receive data is transferred to RDR1 but the RDRF flag is not set. Also,
Framing error
0
[Clearing conditions]
When 0 is written in FER after reading FER = 1
1
[Setting conditions]
When the SCI checks the stop bit at the end of the receive data when reception
ends, and the stop bit is 0.
Notes: 1. The FER flag is not affected and retains its previous state when the RE bit in SCR1 is cleared to 0.
2. In 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is not checked.
If a framing error occurs, the receive data is transferred to RDR1 but the RDRF flag is not set.
Also, subsequent serial reception cannot be continued while the FER flag is set to 1. In synchronous
mode, serial transmission cannot be continued, either.
Overrun error
0
[Clearing conditions]
When 0 is written in ORER after reading ORER = 1
1
[Setting conditions]
When the next serial reception is completed while RDRF = 1
Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCR1 is cleared to 0.
2. The receive data prior to the overrun error is retained in RDR1, and the data received subsequently is lost.
Also, subsequent serial reception cannot be continued while the ORER flag is set to 1. In synchronous
mode, serial transmission cannot be continued, either.
Receive data register full
0
[Clearing conditions]
When 0 is written in RDRF after reading RDRF = 1
1
[Setting conditions]
When serial reception ends normally and receive data is transferred from RSR to RDR
Note: RDR and the RDRF flag are not affected and retain their previous values when an error is detected during reception
or when the RE bit in SCR1 is cleared to 0. If reception of the next data is completed while the RDRF flag is still set
to 1, an overrun error will occur and the receive data will be lost.
[Clearing conditions]
When 0 is written in TDRE after reading TDRE = 1
[Setting conditions]
(1) When the TE bit in SCR1 is 0
(2) When data is transferred from TDR1 to TSR1 and data can be written to TDR1
5
4
3
FER
PER
0
0
0
R/(W)*
R/(W)*
Multiprocessor bit transfer
0
Data with a 0 multiprocessor bit is transmitted (Initial value)
1
Data with a 1 multiprocessor bit is transmitted
Multiprocessor bit
0
[Clearing conditions]*
When data with a 0 multiprocessor bit is received
1
[Setting conditions]
When data with a 1 multiprocessor bit is reveived
Note: * Retains its previous state when the RE bit in SCR1 is cleared to 0 with
multiprocessor format.
Transmit end
0
[Clearing conditions]
(1) When 0 is written in TDRE after reading TDRE = 1
1
[Setting conditions]
(1) When the TE bit in SCR1 is 0
(2) When TDRE = 1 at trasmission of the last bit of a 1-byte serial
transmit character
[Clearing conditions]
When 0 is written in PER after reading PER = 1
[Setting conditions]
When, in reception, the number of 1 bits in the receive data plus the parity bit
does not match the parity setting (even or odd) specified by the O/ bit in SMR
subsequent serial reception cannot be continued while the PER flag is set to 1. In synchronous
mode, serial transmission cannot be continued, either.
*2
2
1
0
TEND
MPB
MPBT
1
0
0
R
R
R/W
(Initial value)
(Initial value)
(Initial value)
*1
(Initial value)
*1
(Initial value)
*1
*2
(Initial value)
(Initial value)
*2
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