Block Diagram - Hitachi H8S/2199 Hardware Manual

Single-chip microcomputer
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16.1.2

Block Diagram

Figure 16.1 shows a block diagram of the Timer X1.
FTIA*
(HSW)
FTIB*
(VD)
FTIC*
(DVCTL)
FTID*
(NHSW)
(DVCFG)
φ / 4
φ / 16
φ / 64
Output comparing output
FTOA
FTOB
[Legend]
TIER
TCSRX
FRC
OCRA
OCRB
TCRX
TOCR
ICRA
ICRB
ICRC
ICRD
Note: * stands for the external terminal.
Rev. 1.0, 02/00, page 314 of 1141
Input
capture
control
: Timer interrupt enabling register
: Timer control/status register X
: Free running counter
: Output comparing register A
: Output comparing register B
: Timer control register X
: Output comparing control register
: Input capture register A
: Input capture register B
: Input capture register C
: Input capture register D
( ) stands for the internal signal.
Figure 16.1 Block Diagram of Timer X1
ICRA
ICRB
ICRC
ICRD
TCRX
OCRB
Comparison circuit
FRC
Comparison circuit
OCRA
TOCR
TCSRX
TIER
Interrupt
request × 7

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