Basic Operational Timing; Access To On-Chip Memory (Ram, Rom) - Hitachi H8/3937 Series Hardware Manual

2.6

Basic Operational Timing

CPU operation is synchronized by a system clock (ø) or a subclock (ø
clock signals see section 4, Clock Pulse Generators. The period from a rising edge of ø or ø
the next rising edge is called one state. A bus cycle consists of two states or three states. The
cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules.
2.6.1

Access to On-Chip Memory (RAM, ROM)

Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing
access in byte or word size. Figure 2-11 shows the on-chip memory access cycle.
ø or ø
SUB
Internal address bus
Internal read signal
Internal data bus
(read access)
Internal write signal
Internal data bus
(write access)
42
T
1
Figure 2-11 On-Chip Memory Access Cycle
Bus cycle
state T
2
Address
Read data
Write data
). For details on these
SUB
state
to
SUB