Hitachi H8S/2199 Hardware Manual page 675

Bit 4    Drum Phase System Z
phase system when computation processing of the drum phase system begins. If 1 is written, it is
reflected on the computation, and then cleared to 0. Set this bit after writing data to DZp.
Bit 4
DZPON Description
0 DZp value is not reflected on Z
1 DZp value is reflected on Z
Bit 3    Drum Speed System Z
speed system when computation processing of the drum speed system begins. If 1 is written, it is
reflected on the computation, and then cleared to 0. Set this bit after writing data to DZs.
Bit 3
DZSON Description
0 DZs value is not reflected on Z
1 DZs value is reflected on Z
Bits 2 to 0    Drum System Output Gain Control Bits (DSG2 to DSG0): Control the gain output
to DRMPWM.
Bit 2 Bit 1
DSG2 DSG1
0 0
1
1 0
1
Note: * Setting optional.
-1
Initialization Bit (DZPON): Reflects the DZp value on Z
-1
of the phase system
-1
of the phase system
-1
Initialization Bit (DZSON): Reflects the DZs value on Z
-1
of the speed system
-1
of the speed system
Bit 0
DSG0 Description
× 1
0
× 2
1
× 4
0
× 8
1
× 16
0
1 (× 32)*
0 (× 64)*
1 Invalid (Do not use this setting)
Rev. 1.0, 02/00, page 669 of 1141
-1
of the
(Initial value)
-1
of the
(Initial value)
(Initial value)