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16.2
Register Descriptions
16.2.1
Free Running Counter (FRC)
Free running counter H (FRCH)
Free running counter L (FRCL)
15
Bit :
Initial value :
0
R/W :
R/W
The FRC is a 16-bit read/write up-counter which counts up by the inputting internal clock/external
clock. The inputting clock is to be selected from the CKS1 and CKS0 of the TCRX.
By the setting of the CCLRA bit of the TCSRX, the FRC can be cleared by comparing match A.
When the FRC overflows (H'FFFF → H'0000), the OVF of the TCSRX will be set to 1.
At this time, when the OVIE of the TIER is being set to 1, an interrupt request will be issued to the
CPU.
Reading/writing can be made from and to the FRC through the CPU at 8-bit or 16-bit.
The FRC is initialized to H'0000 when reset or under the standby mode, watch mode, subsleep
mode, module stop mode or subactive mode.
14
13
12
11
0
0
0
0
R/W
R/W
R/W
R/W
R/W
FRCH
FRC
10
9
8
7
0
0
0
0
R/W
R/W
R/W
R/W
6
5
4
3
2
0
0
0
0
0
R/W
R/W
R/W
R/W
FRCL
Rev. 1.0, 02/00, page 317 of 1141
1
0
0
0
R/W
R/W
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