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27.3.3
Hsync Separation
The Hsync separator separates the Hsync signal from the Csync signal by using the digital H
separation counter, which is a 5-bit up-/down-counter, and the HVTHR register, which holds the
threshold value. The digital H separation counter increments the count when the Csync signal is
high, and decrements the count when the Csync is low. When the count reaches the HVTHR value
while the count is incremented, the SEPH signal is set to 1 and the counter stops until the Csync
signal goes low. When the Csync signal goes low, the counter starts to decrement the count. When
the count reaches H'00, the SEPH signal is reset to 0 and the counter stops until the Csync signal
goes high. Set the HVTHR value so that 2.35-µs equalizing pulses can be detected; that is, that the
Hsync pulses can be continuously detected.
The obtained SEPH signal is sent to the H complement and mask counter. The H complement and
mask counter is reset to 0 when the SEPH signal is input, and increments the count at a frequency
of φ/2 for the SEPH signal cycle period to generate the OSCH signal, HHK signal, and noise
detection window signal. The HHK period is specified by the HM6 to HM0 bits of the HCMMR.
Even if a SEPH signal is input to the counter during this HHK period, the SEPH signal is masked
and the counter is not reset; noise pulses and equalizing pulses during the V blanking period are
eliminated by this function.
The H complement and mask counter has the complement function. If no SEPH signal is input
during the period specified by the HC8 to HC0 bits of the HCMMR, the complement function
generates a complementary pulse and inserts the pulse into the OSCH signal. In this case, the
counter is reset by the complementary pulse, but no HHK signal is generated; the next SEPH
signal input resets the counter, and the counter is synchronized with the SEPH signal. For the
timing, refer to figure 27.12.
Note: In a weak field, equalizing pulses are not detected in some cases because the pulses have a
short duration of 2.35 µs. If equalizing pulses, which are input at the same timing as the
Hsync pulses, are not detected, a phase-difference error between the Hsync and Vsync
occurs at a rising edge of the Vsync signal. Such an error will cause incorrect field
detection in the sync separator and incorrect line detection by the OSD or data slicer. In
such a weak field, adjust the HVTHR value so that equalizing pulses are not detected.
Note that while equalizing pulses are not detected, complementary pulses are inserted
repeatedly and an Hsync-Vsync phase-difference error occurs at a rising edge of the
Vsync signal, even in a field that is not weak. To avoid this, set the HHKON bit (bit 2) of
the SEPCR to 1 to operate the HHK function when complementary pulses are generated
three successive times. For the timing, refer to figure 27.6.
Rev. 1.0, 02/00, page 791 of 1141
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