Hitachi H8S/2199 Hardware Manual page 1040

H'D101: Timer Control/Status Register X TCSRX: Timer X1
7
Bit :
ICFA
Initial value :
0
R/(W)*
R/W :
Input capture flag A
0
1
Note: * Only 0 can be written to bits 7 to 1 to clear the flags.
Rev. 1.0, 02/00, page 1038 of 1141
6 5
ICFB ICFC ICFD
0 0
R/(W)* R/(W)* R/(W)*
Input capture flag D
0
1
Input capture flag C
0 [Clearing conditions]
When 0 is written to ICFC after reading
ICFC = 1
1 [Setting conditions]
When input capture signal is generated
Input capture flag B
0 [Clearing conditions]
When 0 is written to ICFB after reading
ICFB = 1
1 [Setting conditions]
When FRC value is transferred to ICRB by
input capture signal
[Clearing conditions]
When 0 is written to ICFA after reading
ICFA = 1
[Setting conditions]
When FRC value is transferred to ICRA by
input capture signal
4 3 2
OCFA OCFB
0 0 0
R/(W)* R/(W)*
Timer overflow
Output compare flag B
0
1
Output compare flag A
0 [Clearing conditions]
When 0 is written to OCFA after reading
OCFA = 1
1 [Setting conditions]
When FRC = OCRA
[Clearing conditions]
When 0 is written to ICFD after reading
ICFD = 1
[Setting conditions]
When input capture signal is generated
(Initial value)
(Initial value)
(Initial value)
1 0
OVF CCLRA
0 0
R/(W)* R/ W
Counter clear
0 FRC clearing is disabled
1 FRC clearing is enabled
0 [Clearing conditions]
When 0 is written to OVF after reading
OVF = 1
1 [Setting conditions]
When FRC changes from H'FFFF to
H'0000
[Clearing conditions]
When 0 is written to OCFB after reading
OCFB = 1
(Initial value)
[Setting conditions]
When FRC = OCRB
(Initial value)
(Initial value)
(Initial value)
(Initial value)