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21.1.3
Pin Configuration
Table 21.1 shows the pin configuration of the prescalar unit.
Table 21.1 Pin Configuration
Name
Input capture input
Frequency division clock
output
21.1.4
Register Configuration
Table 21.2 shows the register configuration of the prescalar unit.
Table 21.2 Register Configuration
Name
Input capture register 1
Prescalar unit
control/status register
Note:
*
Lower 16 bits of the address.
Abbrev.
I/O
,&
Input
TMOW
Output
Abbrev.
R/W
ICR1
R
PCSR
R/W
Function
Prescalar unit input capture input pin
Prescalar unit frequency division clock
output pin
Size
Initial Value
Byte
H'00
Byte
H'08
Rev. 1.0, 02/00, page 389 of 1141
Address*
H'D12C
H'D12D
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