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Figure 6.3 shows the timing of IRQnF setting.
Internal φ
IRQn
input pin
IRQnF
The vector num ber s f or I RQ 5 t o I RQ 0 i nt er r upt except i on handl i ng ar e 21 t o 26.
U pon det ect i on of I RQ 5 t o I RQ 0 i nt er r upt s , t he appl i cabl e pi n i s s et i n t he por t r egi s t er 1 ( PM R1)
as ,54Q pi n.
6.3.2
Internal Interrupts
There are 38 sources for internal interrupts from on-chip supporting modules.
• For each on-chip supporting module there are flags that indicate the interrupt request status,
and enable bits that select enabling or disabling of these interrupts. If any one of these is set to
1, an interrupt request is issued to the interrupt controller.
• The interrupt control level can be set by means of ICR.
• The NMI is the highest priority interrupt and is always accepted regardless of the control mode
and CPU interrupt mask bit. In this LSI, NMIs are used as interrupts generated by the
watchdog timer
Figure 6.3 Timing of IRQnF Setting
Rev. 1.0, 02/00, page 107 of 1141
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