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MCU operating modes (modes 1 to 4) are provided, offering a choice of initial data bus width and address space size. With these features, the H8/3008 enables easy implementation of compact, high-performance systems. This manual describes the H8/3008 hardware. For details of the instruction set, refer to the H8/300H Series Programming Manual.
18.4.1 Transition to Software Standby Mode ..............444 18.4.2 Exit from Software Standby Mode................ 445 18.4.3 Selection of Waiting Time for Exit from Software Standby Mode ...... 445 18.4.4 Sample Application of Software Standby Mode........... 447 18.4.5 Note ........................447 18.5 Hardware Standby Mode....................
Appendix G Package Dimensions ..................619 Appendix H Comparison of H8/300H Series Product Specifications ....622 Differences between H8/3067 and H8/3062 Series, H8/3048 Series, H8/3006 and H8/3007, and H8/3008.................. 622 Comparison of Pin Functions of 100-Pin Package Products (FP-100B, TFP-100B)..625...
Section 1 Overview Overview The H8/3008 is a microcontroller (MCU) that integrates system supporting functions together with an H8/300H CPU core having an original Hitachi architecture. The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for speed.
Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16 bits) • Bit accumulator function Bit manipulation instructions with register-indirect specification of bit positions Memory H8/3008 • RAM: 4 kbytes • Interrupt Seven external interrupt pins: NMI, IRQ...
Feature Description • 16-bit timer, Three 16-bit timer channels, capable of processing up to six pulse outputs or 3 channels six pulse inputs • 16-bit timer counter (channels 0 to 2) • Two multiplexed output compare/input capture pins (channels 0 to 2) •...
Programmable system clock frequency division • Other features On-chip clock pulse generator Product lineup Package Product Type Model (Hitachi Package Code) H8/3008 5 V operation HD6413008F 100-pin QFP (FP-100B) HD6413008TE 100-pin TQFP (TFP-100B) HD6413008FP 100-pin QFP (FP-100A) 3 V operation HD6413008VF...
Block Diagram Figure 1.1 shows an internal block diagram. Port 3 Port 4 Address bus Data bus (upper) Data bus (lower) EXTAL XTAL STBY H8/300H CPU RESO φ/P6 Interrupt controller BACK/P6 BREQ/P6 WAIT/P6 Watchdog timer ADTRG/CS (WDT) /IRQ /IRQ 16-bit timer unit /IRQ Serial communication interface...
1.3.1 Pin Arrangement The pin arrangement of the H8/3008 is shown in figures 1.2 and 1.3. Differences in the H8/3008 pin arrangements are shown in table 1.2. Except for the differences shown in table 1.2, the pin arrangements are the same.
Note: * V pin in 5 V operation models, V pin in 3 V operation models. 0.1 µF An external capacitor must be connected to the V pin. Figure 1.2 Pin Arrangement of H8/3008 (FP-100B or TFP-100B Package, Top View)
/TIOCA /TIOCB 0.1 µF Note: * V pin in 5 V operation models, V pin in 3 V operation models. An external capacitor must be connected to the V pin. Figure 1.3 Pin Arrangement of H8/3008 (FP-100A Package, Top View)
1.3.2 Pin Functions Table 1.3 summarizes the pin functions. The 5 V operation models have a V pin, and require the connection of an external capacitor. Table 1.3 Pin Functions Pin No. FP-100B Type Symbol TFP-100B FP-100A I/O Name and Function Power 1, 35, 3, 37,...
Pin No. FP-100B Type Symbol TFP-100B FP-100A I/O Name and Function System Input Reset input: When driven low, this pin resets control the chip. This pin must be driven low at power- RESO Output Reset output: Outputs the reset signal generated by the watchdog timer to external devices STBY...
Pin No. FP-100B Type Symbol TFP-100B FP-100A I/O Name and Function 16-bit TCLKD to 96 to 93 98 to95 Input Clock input D to A: External clock inputs timer TCLKA TIOCA 99, 97, 95 1, 99, 97 Input/ Input capture/output compare A2 to A0: TIOCA output GRA2 to GRA0 output compare or input...
Pin No. FP-100B Type Symbol TFP-100B FP-100A I/O Name and Function Analog Input Ground pin for the A/D and D/A converters. power Connect to system ground (0 V). supply Input Reference voltage input pin for the A/D and D/A converters. Connect to the system power supply when not using the A/D and D/A converters.
1.3.3 Pin Assignments in Each Mode Table 1.4 lists the pin assignments in each mode. Table 1.4 Pin Assignments in Each Mode (FP-100B, TFP-100B, or FP-100A) Pin No. Pin Name FP-100B TFP-100B FP-100A Mode 1 Mode 2 Mode 3 Mode 4 TMIO TMIO TMIO...
Section 2 CPU Overview The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. 2.1.1 Features The H8/300H CPU has the following features.
• Two CPU operating modes Normal mode Advanced mode • Low-power mode Transition to power-down state by SLEEP instruction 2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8/300H has the following enhancements. • More general registers Eight 16-bit registers have been added.
Address Space Figure 2.2 shows a simple memory map for the H8/3008. The H8/300H CPU can address a linear address space with a maximum size of 64 kbytes in normal mode, and 16 Mbytes in advanced mode. For further details see section 3.6, Memory Map in Each Operating Mode.
Register Configuration 2.4.1 Overview The H8/300H CPU has the internal registers shown in figure 2.3. There are two types of registers: general registers and control registers. General Registers (ERn) (SP) Control Registers (CR) 6 5 4 3 2 1 0 I UI H U N Z V C Legend: Stack pointer...
2.4.2 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used without distinction between data registers and address registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or as address registers, they are designated by the letters ER (ER0 to ER7).
Free area SP (ER7) Stack area Figure 2.5 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC) and the 8-bit condition code register (CCR). Program Counter (PC): This 24-bit counter indicates the address of the next instruction the CPU will execute.
Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0—Carry Flag (C): Set to 1 when a carry is generated by execution of an operation, and cleared to 0 otherwise. Used by: •...
Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.
General Data Type Register Data Format Word data Word data Longword data Legend: ERn: General register General register E General register R MSB: Most significant bit LSB: Least significant bit Figure 2.7 General Register Data Formats 2.5.2 Memory Data Formats Figure 2.8 shows the data formats on memory.
Data Type Address Data Format 1-bit data Address L Byte data Address L Word data Address 2M Address 2M + 1 Address 2N Longword data Address 2N + 1 Address 2N + 2 Address 2N + 3 Figure 2.8 Memory Data Formats When ER7 (SP) is used as an address register to access the stack, the operand size should be word size or longword size.
Notes: 1. POP.W Rn is identical to MOV.W @SP+, Rn. PUSH.W Rn is identical to MOV.W Rn, @–SP. POP.L ERn is identical to MOV.L @SP+, Rn. PUSH.L ERn is identical to MOV.L Rn, @–SP. 2. Not available in the H8/3008. 3. Bcc is a generic branching instruction.
2.6.3 Tables of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The operation notation used in these tables is defined next. Operation Notation General register (destination)* General register (source)* General register* General register (32-bit register or address register)* (EAd) Destination operand (EAs)
Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. (EAs) → Rd MOVFPE Cannot be used in the H8/3008. Rs → (EAs) MOVTPE Cannot be used in the H8/3008.
Table 2.4 Arithmetic Operation Instructions Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd ADD,SUB B/W/L Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from data in a general register.
Instruction Size* Function Rd ÷ Rs → Rd DIVXU Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder Rd ÷...
Table 2.5 Logic Operation Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd B/W/L Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd B/W/L Performs a logical OR operation on a general register and another general register or immediate data.
Table 2.7 Bit Manipulation Instructions Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower 3 bits of a general register.
Instruction Size* Function C ∨ (<bit-No.> of <EAd>) → C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. C ∨...
Table 2.8 Branching Instructions Instruction Size Function — Branches to a specified address if address specified condition is met. The branching conditions are listed below. Mnemonic Description Condition BRA (BT) Always (true) Always BRN (BF) Never (false) Never C ∨ Z = 0 High C ∨...
Table 2.9 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling — Returns from an exception-handling routine SLEEP — Causes a transition to the power-down state (EAs) → CCR Moves the source operand contents to the condition code register. The condition code register size is one byte, but in transfer from memory, data is read by word access.
Operation field only NOP, RTS, etc. Operation field and register fields ADD.B Rn, Rm, etc. Operation field, register fields, and effective address extension MOV.B @(d:16, Rn), Rm EA (disp) Operation field, effective address extension, and condition field EA (disp) BRA d:8 Figure 2.9 Instruction Formats 2.6.5 Notes on Use of Bit Manipulation Instructions...
Before Execution of BCLR Instruction Input/output Input Input Output Output Output Output Output Output Execution of BCLR Instruction BCLR #0, P4DDR Execute BCLR instruction on DDR After Execution of BCLR Instruction Input/output Output Output Output Output Output Output Output Input Explanation: To execute the BCLR instruction, the CPU begins by reading P4DDR.
Addressing Modes and Effective Address Calculation 2.7.1 Addressing Modes The H8/300H CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program- counter relative and memory indirect.
4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn: • Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) the lower 24 bits of which contain the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents (32 bits) and the sum is stored in the address register.
extended to 24 bits and added to the 24-bit PC contents to generate a 24-bit branch address. The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes (–16383 to +16384 words) from the branch instruction.
Processing States 2.8.1 Overview The H8/300H CPU has five processing states: the program execution state, exception-handling state, power-down state, reset state, and bus-released state. The power-down state includes sleep mode, software standby mode, and hardware standby mode. Figure 2.11 classifies the processing states.
2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from the exception vector table and branches to that address. In interrupt and trap exception handling the CPU references the stack pointer (ER7) and saves the program counter and condition code register.
Bus request End of bus release Program execution state End of bus SLEEP release instruction with SSBY = 0 request Exception handling source Bus-released state Sleep mode End of SLEEP instruction Interrupt source exception with SSBY = 1 handling NMI, IRQ , IRQ , or IRQ interrupt Exception-handling state Software standby mode...
Figure 2.15 shows the on-chip memory access cycle. Figure 2.16 indicates the pin states. The H8/3008 has a function for changing the method of outputting addresses from the address pins. For details see section 6.3.5, Address Output Method.
Bus cycle T state T state φ Internal address bus Address Internal read signal Internal data bus Read data (read access) Internal write signal Internal data bus Write data (write access) Figure 2.15 On-Chip Memory Access Cycle φ Address bus Address RD HWR LWR High...
Bus cycle T state T state T state φ Address Address bus Internal read signal Read access Internal data bus Read data Internal write signal Write access Internal data bus Write data Figure 2.17 Access Cycle for On-Chip Supporting Modules φ...
Operating Mode Selection The H8/3008 has four operating modes (modes 1 to 4) that are selected by the mode pins (MD ) as indicated in table 3.1. The input at these pins determines the size of the address space and the initial bus mode.
1 Mbyte. Modes 3 and 4 support a maximum address space of 16 Mbytes. The H8/3008 can be used only in modes 1 to 4. The inputs at the mode pins must select one of these four modes. The inputs at the mode pins must not be changed during operation. Set the reset state before changing the inputs at these pins.
MDS0 are read-only bits. The mode pin (MD to MD ) levels are latched into these bits when MDCR is read. System Control Register (SYSCR) SYSCR is an 8-bit register that controls the operation of the H8/3008. SSBY STS2 STS1 STS0...
Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the length of time the CPU and on-chip supporting modules wait for the internal clock oscillator to settle when software standby mode is exited by an external interrupt. When using a crystal oscillator, set these bits so that the waiting time will be at least 7 ms at the system clock rate.
Bit 1—Software Standby Output Port Enable (SSOE): Specifies whether the address bus and to CS , AS, RD, HWR , LWR ) are kept as outputs or fixed high, or bus control signals (CS placed in the high-impedance state in software standby mode. Bit 1 SSOE Description...
3.4.5 Modes 5 to 7 These modes cannot be used in the H8/3008. Pin settings must not be made for these modes. Pin Functions in Each Operating Mode The pin functions of ports 1 to 5 and port A vary depending on the operating mode. Table 3.3 indicates their functions in each operating mode.
Memory Map in Each Operating Mode Figures 3.1 and 3.2 show memory maps of the H8/3008. In the expanded modes, the address space is divided into eight areas. The initial bus mode differs between modes 1 and 2, and also between modes 3 and 4.
H'FFFFF H'FF8000 H'FFEF1F H'FFEF20 On-chip RAM* H'FFFF00 H'FFFF1F H'FFFF20 Internal I/O registers (2) H'FFFFE9 H'FFFFEA External address space H'FFFFFF Note: * External addresses can be accessed by disabling on-chip RAM. Figure 3.1 Memory Map of H8/3008 in Each Operating Mode...
Section 4 Exception Handling Overview 4.1.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, interrupt, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in priority order.
4.1.3 Exception Vector Table The exception sources are classified as shown in figure 4.1. Different vectors are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. • Reset External interrupts: NMI, IRQ to IRQ Exception •...
Table 4.2 Exception Vector Table Vector Address* Exception Source Vector Number Advanced Mode Normal Mode Reset H'0000 to H'0003 H'0000 to H'0001 Reserved for system use H'0004 to H'0007 H'0002 to H'0003 H'0008 to H'000B H'0004 to H'0005 H'000C to H'000F H'0006 to H'0007 H'0010 to H'0013 H'0008 to H'0009...
Reset 4.2.1 Overview A reset is the highest-priority exception. When the RES pin goes low, all processing halts and the chip enters the reset state. A reset initializes the internal state of the CPU and the registers of the on-chip supporting modules. Reset exception handling begins when the RES pin changes from low to high.
Internal Vector fetch processing Prefetch of first program instruction φ Address bus High to D (1), (3) Address of reset exception handling vector: (1) = H'000000, (3) = H'000002 (2), (4) Start address (contents of reset exception handling vector address) Start address First instruction of program Note: After a reset, the wait-state controller inserts three wait states in every bus cycle.
Interrupts Interrupt exception handling can be requested by seven external sources (NMI, IRQ to IRQ ), and 27 internal sources in the on-chip supporting modules. Figure 4.4 classifies the interrupt sources and indicates the number of interrupts of each type. The on-chip supporting modules that can request interrupts are the watchdog timer (WDT), 16-bit timer, 8-bit timer, serial communication interface (SCI), and A/D converter.
Stack Status after Exception Handling Figure 4.5 shows the stack after completion of trap instruction exception handling and interrupt exception handling. → SP–4 SP (ER7) SP–3 SP+1 SP–2 SP+2 SP–1 SP+3 SP (ER7) → Stack area SP+4 Even address Before exception handling After exception handling Pushed on stack a.
Notes on Stack Usage When accessing word data or longword data, the H8/3008 regards the lowest address bit as 0. The stack should always be accessed by word access or longword access, and the value of the stack pointer (SP:ER7) should always be kept even.
H'FFFEFA H'FFFEFB H'FFFEFC H'FFFEFD H'FFFEFE H'FFFEFF TRAPA instruction executed MOV. B R1L, @-ER7 SP set to H'FFFEFF Data saved above SP CCR contents lost Legend CCR: Condition code register Program counter R1L: General register R1L Stack pointer Note: The diagram illustrates modes 3 and 4. Figure 4.6 Operation when SP Value is Odd...
Section 5 Interrupt Controller Overview 5.1.1 Features The interrupt controller has the following features: • Interrupt priority registers (IPRs) for setting interrupt priorities Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis in interrupt priority registers A and B (IPRA and IPRB). •...
SYSCR is initialized to H'09 by a reset and in hardware standby mode. It is not initialized in software standby mode. SSBY STS2 STS1 STS0 NMIEG SSOE RAME Initial value Read/Write RAM enable Software standby output port enable NMI edge select Standby timer Selects the NMI input edge select 2 to 0...
Interrupt Priority Register A (IPRA): IPRA is an 8-bit readable/writable register in which interrupt priority levels can be set. IPRA7 IPRA6 IPRA5 IPRA4 IPRA3 IPRA2 IPRA1 IPRA0 Initial value Read/Write Priority level A0 Selects the priority level of 16-bit timer channel 2 interrupt requests...
Bit 7—Priority Level A7 (IPRA7): Selects the priority level of IRQ interrupt requests. Bit 7 IPRA7 Description interrupt requests have priority level 0 (low priority) (Initial value) interrupt requests have priority level 1 (high priority) Bit 6—Priority Level A6 (IPRA6): Selects the priority level of IRQ interrupt requests.
Bit 2—Priority Level A2 (IPRA2): Selects the priority level of 16-bit timer channel 0 interrupt requests. Bit 2 IPRA2 Description 16-bit timer channel 0 interrupt requests have priority level 0 (low priority) (Initial value) 16-bit timer channel 0 interrupt requests have priority level 1 (high priority) Bit 1—Priority Level A1 (IPRA1): Selects the priority level of 16-bit timer channel 1 interrupt requests.
Interrupt Priority Register B (IPRB): IPRB is an 8-bit readable/writable register in which interrupt priority levels can be set. IPRB7 IPRB6 — — IPRB3 IPRB2 — — Initial value Read/Write Reserved bit Priority level B2 Selects the priority level of SCI channel 1 interrupt requests Priority level B3 Selects the priority level of SCI...
Bit 6—Priority Level B6 (IPRB6): Selects the priority level of 8-bit timer channel 2, 3 interrupt requests. Bit 6 IPRB6 Description 8-bit timer channel 2 and 3 interrupt requests have priority level 0 (low priority) (Initial value) 8-bit timer channel 2 and 3 interrupt requests have priority level 1 (high priority) Bits 5 and 4—Reserved: These bits can be written and read, but they do not affect interrupt priority.
— — IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial value Read/Write — — R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * Reserved bits IRQ to IRQ flags These bits indicate IRQ to IRQ flag interrupt request status Note: Only 0 can be written, to clear flags.
Bits 7 and 6—Reserved: These bits can be written and read, but they do not enable or disable interrupts. Bits 5 to 0—IRQ to IRQ Enable (IRQ5E to IRQ0E): These bits enable or disable to IRQ interrupts. Bits 5 to 0 IRQ5E to IRQ0E Description to IRQ interrupts are disabled...
Interrupt Sources The interrupt sources include external interrupts (NMI, IRQ to IRQ ) and 27 internal interrupts. 5.3.1 External Interrupts There are seven external interrupts: NMI, and IRQ to IRQ . Of these, NMI, IRQ , IRQ , and can be used to exit software standby mode. NMI: NMI is the highest-priority interrupt and is always accepted, regardless of the states of the I and UI bits in CCR.
Figure 5.3 shows the timing of the setting of the interrupt flags (IRQnF). φ IRQn input pin IRQnF Note: n = 5 to 0 Figure 5.3 Timing of Setting of IRQnF Interrupts IRQ to IRQ have vector numbers 12 to 17. These interrupts are detected regardless of whether the corresponding pin is set for input or output.
Table 5.3 Interrupt Sources, Vector Addresses, and Priority Vector Address* Vector Interrupt Source Origin Number Advanced Mode Normal Mode Priority External H'001C to H'001F H'000E to H'000F — High pins H'0030 to H'0033 H'0018 to H'0019 IPRA7 H'0034 to H0037 H'001A to H'001B IPRA6 H'0038 to H'003B H'001C to H'001D...
Vector Address* Vector Interrupt Source Origin Number Advanced Mode Normal Mode Priority IMIA2 16-bit timer H'0080 to H'0083 H'0040 to H'0041 IPRA0 High (compare match/ channel 2 input capture A2) IMIB2 H'0084 to H'0087 H'0042 to H'0043 (compare match/ input capture B2) OVI2 (overflow 2) H'0088 to H'008B H'0044 to H'0045...
Vector Address* Vector Interrupt Source Origin Number Advanced Mode Normal Mode Priority ERI0 H'00D0 to H'00D3 H'0068 to H'0069 IPRB3 High (receive error 0) channel 0 RXI0 (receive H'00D4 to H'00D7 H'006A to H'006B data full 0) TXI0 (transmit H'00D8 to H'00DB H'006C to H'006D data empty 0) TEI0...
Interrupt Handling Process The H8/3008 handles interrupts differently depending on the setting of the UE bit. When UE = 1, interrupts are controlled by the I bit. When UE = 0, interrupts are controlled by the I and UI bits.
Program execution state Interrupt requested? Pending Priority level 1? TEI1 TEI1 I = 0 Save PC and CCR ← Read vector address Branch to interrupt service routine Figure 5.4 Process Up to Interrupt Acceptance when UE = 1...
• If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. • When the interrupt controller receives one or more interrupt requests, it selects the highest- priority request, following the IPR interrupt priority settings, and holds other requests pending.
← All interrupts are Only NMI, IRQ , and ← ← 1, UI unmasked IRQ are unmasked Exception handling, ← ← or I 1, UI ← ← Exception handling, ← or UI All interrupts are masked except NMI Figure 5.5 Interrupt Masking State Transitions (Example) Figure 5.6 is a flowchart showing how interrupts are accepted when UE = 0.
Program execution state Interrupt requested? Pending Priority level 1? TEI1 TEI1 I = 0 I = 0 UI = 0 Save PC and CCR ← ← 1, UI Read vector address Branch to interrupt service routine Figure 5.6 Process Up to Interrupt Acceptance when UE = 0...
5.4.2 Interrupt Exception Handling Sequence Figure 5.7 shows the interrupt exception handling sequence in mode 2 when the program code and stack are in an external memory area accessed in two states via a 16-bit bus. Figure 5.7 Interrupt Exception Handling Sequence...
5.4.3 Interrupt Response Time Table 5.5 indicates the interrupt response time from the occurrence of an interrupt request until the first instruction of the interrupt service routine is executed. Table 5.5 Interrupt Response Time External Memory 8-Bit Bus 16-Bit Bus On-Chip Item Memory...
Usage Notes 5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction When an instruction clears an interrupt enable bit to 0 to disable the interrupt, the interrupt is not disabled until after execution of the instruction is completed. If an interrupt occurs while a BCLR, MOV, or other instruction is being executed to clear its interrupt enable bit to 0, at the instant when execution of the instruction ends the interrupt is still enabled, so its interrupt exception handling is carried out.
5.5.2 Instructions that Inhibit Interrupts The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs, after determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the CPU is currently executing one of these interrupt-inhibiting instructions, however, when the instruction is completed the CPU always continues by executing the next instruction.
Section 6 Bus Controller Overview The H8/3008 has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily.
6.1.2 Block Diagram Figure 6.1 shows a block diagram of the bus controller. to CS ABWCR ASTCR Area Internal address bus Internal signals CSCR decoder Chip select ADRCR Bus mode control signal control signals Bus size control signal Access state control signal Bus control Wait request signal circuit...
6.1.3 Pin Configuration Table 6.1 summarizes the input/output pins of the bus controller. Table 6.1 Bus Controller Pins Name Abbreviation Function to CS Chip select 0 to 7 Output Strobe signals selecting areas 0 to 7 Address strobe Output Strobe signal indicating valid address output on the address bus Read Output...
6.1.4 Register Configuration Table 6.2 summarizes the bus controller’s registers. Table 6.2 Bus Controller Registers Address* Name Abbreviation Initial Value H'EE020 Bus width control register ABWCR H'FF* H'EE021 Access state control register ASTCR H'FF H'EE022 Wait control register H WCRH H'FF H'EE023 Wait control register L...
Bits 7 to 0—Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select 8-bit access or 16-bit access for the corresponding areas. Bits 7 to 0 ABW7 to ABW0 Description Areas 7 to 0 are 16-bit access areas Areas 7 to 0 are 8-bit access areas ABWCR specifies the data bus width of external memory areas.
6.2.3 Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. On-chip memory and registers are accessed in a fixed number of states that does not depend on WCRH/WCRL settings.
Bits 5 and 4—Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set to 1. Bit 5 Bit 4 Description Program wait not inserted when external space area 6 is accessed...
WCRL Initial value Read/Write Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set to 1.
Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1. Bit 3 Bit 2 Description Program wait not inserted when external space area 1 is accessed...
6.2.4 Bus Release Control Register (BRCR) BRCR is an 8-bit readable/writable register that enables address output on bus lines A to A enables or disables release of the bus to an external device. A23E A22E A21E A20E — — — BRLE Initial value Modes...
Bit 5—Address 21 Enable (A21E): Enables PA to be used as the A address output pin. Writing 0 in this bit enables A output from PA . In modes other than 3 and 4, this bit cannot be modified and PA has its ordinary port functions.
BCR is initialized to H'C6 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7—Idle Cycle Insertion 1 (ICIS1): Selects whether one idle cycle state is to be inserted between bus cycles in case of consecutive external read cycles for different areas. Bit 7 ICIS1 Description...
Bit 0—WAIT Pin Enable (WAITE): Enables or disables wait insertion by means of the WAIT pin. Bit 0 WAITE Description WAIT pin wait input is disabled, and the WAIT pin can be used as an input/output port (Initial value) WAIT pin wait input is enabled 6.2.6 Chip Select Control Register (CSCR) CSCR is an 8-bit readable/writable register that enables or disables output of chip select signals...
6.2.7 Address Control Register (ADRCR) ADRCR is an 8-bit readable/writable register that selects either address update mode 1 or address update mode 2 as the address output method. — — — — — — — ADRCTL Initial value Read/Write — —...
Operation 6.3.1 Area Division The external address space is divided into areas 0 to 7. Each area has a size of 128 kbytes in the 1- Mbyte modes, or 2 Mbytes in the 16-Mbyte modes. Figure 6.2 shows a general view of the memory map.
H'000000 Area 0 Area 0 2 Mbytes 2 Mbytes H'1FFFFF H'200000 Area 1 Area 1 2 Mbytes 2 Mbytes H'3FFFFF H'400000 Area 2 2 Mbytes Area 2 H'5FFFFF 8 Mbytes H'600000 Area 3 2 Mbytes H'7FFFFF H'800000 Area 4 2 Mbytes H'9FFFFF H'A00000 Area 5...
6.3.2 Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller.
6.3.3 Memory Interfaces As its memory interface, the H8/3008 has only a basic bus interface that allows direct connection of ROM, SRAM, and so on. It is not possible to select a DRAM interface that allows direct connection of DRAM, or a burst ROM interface that allows direct connection of burst ROM.
6.3.5 Address Output Method The H8/3008 provides a choice of two address update methods: either the same method as in the previous H8/300H Series (address update mode 1), or a method in which address updating is restricted to external space accesses (address update mode 2).
• ADRCR is allocated to address H'FEE01E. In the H8/3062F-ZTAT, the corresponding address is empty space, but it is necessary to confirm that no accesses are made to H'FEE01E in the program. • When address update mode 2 is selected, the address in an internal space (on-chip memory or internal I/O) access cycle is not output externally.
Basic Bus Interface 6.4.1 Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 6.4). 6.4.2 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (D to D...
In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd address.
The initial state of each area is basic bus interface, three-state access space. The initial bus width is selected according to the operating mode. Areas 0 to 6: In the H8/3008, the entire space of areas 0 to 6 is external space. When area 0 to 6 external space is accessed, the CS to CS pin signals respectively can be output.
6.4.5 Basic Bus Control Signal Timing 8-Bit, Three-State-Access Areas: Figure 6.9 shows the timing of bus control signals for an 8-bit, three-state-access area. The upper data bus (D to D ) is used in accesses to these areas. The LWR pin is always high. Wait states can be inserted. Bus cycle φ...
8-Bit, Two-State-Access Areas: Figure 6.10 shows the timing of bus control signals for an 8-bit, ) is used in accesses to these areas. The LWR two-state-access area. The upper data bus (D to D pin is always high. Wait states cannot be inserted. Bus cycle φ...
16-Bit, Three-State-Access Areas: Figures 6.11 to 6.13 show the timing of bus control signals for a 16-bit, three-state-access area. In these areas, the upper data bus (D to D ) is used in accesses to even addresses and the lower data bus (D to D ) in accesses to odd addresses.
Bus cycle φ Address bus Odd external address in area n to D Invalid Read access to D Valid High Write access to D Undetermined data to D Valid Note: n = 7 to 0 Figure 6.12 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (2) (Byte Access to Odd Address)
Bus cycle φ Address bus External address in area n Valid to D Read access to D Valid Write access Valid to D to D Valid Note: n = 7 to 0 Figure 6.13 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (3) (Word Access)
16-Bit, Two-State-Access Areas: Figures 6.14 to 6.16 show the timing of bus control signals for a 16-bit, two-state-access area. In these areas, the upper data bus (D to D ) is used in accesses to even addresses and the lower data bus (D to D ) in accesses to odd addresses.
Bus cycle φ Address bus Odd external address in area n to D Read access Invalid to D Valid High Write access to D Undetermined data to D Valid Note: n = 7 to 0 Figure 6.15 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (2) (Byte Access to Odd Address)
(Word Access) 6.4.6 Wait Control When accessing external space, the H8/3008 can extend the bus cycle by inserting wait states (T There are two ways of inserting wait states: program wait insertion and pin wait insertion using the WAIT pin.
Pin Wait Insertion: Setting the WAITE bit in BCR to 1 enables wait insertion by means of the WAIT pin. When external space is accessed in this state, a program wait is first inserted. If the WAIT pin is low at the falling edge of φ in the last T or T state, another T state is inserted.
Idle Cycle 6.5.1 Operation When the H8/3008 chip accesses external space, it can insert a 1-state idle cycle (T ) between bus cycles in the following cases: when read accesses between different areas occur consecutively, and when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, which has a long output floating time, and high-speed memory, I/O interfaces, and so on.
Bus cycle A Bus cycle B Bus cycle A Bus cycle B φ φ Address bus Address bus Data bus Data bus Data collision Long buffer-off time (a) Idle cycle not inserted (b) Idle cycle inserted Figure 6.19 Example of Idle Cycle Operation (ICIS0 = 1) Usage Note: When non-insertion of an idle cycle is specified, the rise (negation) of RD and fall (assertion) of CS may occur simultaneously.
6.5.2 Pin States in Idle Cycle Table 6.5 shows the pin states in an idle cycle. Table 6.5 Pin States in Idle Cycle Pins Pin State to A Next cycle address value to D High impedance High High High High High Bus Arbiter The bus controller has a built-in bus arbiter that arbitrates between different bus masters.
BREQ signal goes high. While the bus is released to an external bus master, the H8/3008 chip holds the address bus, data bus, bus control signals (AS, RD, HWR, and LWR), and chip select signals (CSn: n = 7 to 0) in the high-impedance state, and holds the BACK pin in the low output state.
CPU cycles External bus released CPU cycles φ High-impedance Address Address bus High-impedance Data bus High-impedance High-impedance High High-impedance HWR, LWR BREQ BACK Minimum 3 cycles Figure 6.21 Example of External Bus Master Operation When making a transition to software standby mode, if there is contention with a bus request from an external bus master, the BACK and strobe states may be indefinite when the transition is made.
Register and Pin Input Timing 6.7.1 Register Write Timing ABWCR, ASTCR, WCRH, and WCRL Write Timing: Data written to ABWCR, ASTCR, WCRH, and WCRL takes effect starting from the next bus cycle. Figure 6.22 shows the timing when an instruction fetched from area 0 changes area 0 from three-state access to two-state access. φ...
φ Address bus BRCR address to PA to A High-impedance Figure 6.24 BRCR Write Timing BREQ Pin Input Timing 6.7.2 After driving the BREQ pin low, hold it low until BACK goes low. If BREQ returns to the high level before BACK goes lows, the bus arbiter may operate incorrectly. To terminate the external-bus-released state, hold the BREQ signal high for at least three states.
Section 7 I/O Ports Overview The H8/3008 has six input/output ports (ports 4, 6, 8, 9, A, and B) and one input-only port (port 7). Table 7.1 summarizes the port functions. The pins in each port are multiplexed as shown in table 7.1.
Expanded Modes Port Description Pins Mode 1 Mode 2 Mode 3 Mode 4 Port 8 • 5-bit I/O port DDR = 0: generic input DDR = 1 (reset value): CS output • P8 input, CS to P8 have /IRQ output, external trigger input (ADTRG) to A/D ADTRG schmitt inputs converter, and generic input...
Expanded Modes Port Description Pins Mode 1 Mode 2 Mode 3 Mode 4 Port B • 8-bit I/O port TPC output (TP to TP ) and generic input/output /TMIO TPC output (TP to TP ), 8-bit timer input and output (TMIO ), CS to CS , TMIO...
7.1. The pin functions differ depending on the operating mode. In the H8/3008, when the bus width control register (ABWCR) designates areas 0 to 7 all as 8-bit- access areas, the chip operates in 8-bit bus mode and port 4 is a generic input/output port. When at least one of areas 0 to 7 is designated as a 16-bit-access area, the chip operates in 16-bit bus mode and port 4 becomes part of the data bus.
7.2.2 Register Descriptions Table 7.2 summarizes the registers of port 4. Table 7.2 Port 4 Registers Address* Name Abbreviation Initial Value H'EE003 Port 4 data direction register P4DDR H'00 H'FFFD3 Port 4 data register P4DR H'00 H'EE03E Port 4 input pull-up MOS control P4PCR H'00 register...
in P4DDR is set to 1, if port 4 is read the value of the corresponding P4DR bit is returned. When a bit in P4DDR is cleared to 0, if port 4 is read the corresponding pin logic level is read. Initial value Read/Write Port 4 data 7 to 0...
Port 6 7.3.1 Overview Port 6 is an 8-bit input/output port that is also used for input and output of bus control signals (LWR, HWR, RD, AS, BACK, BREQ, WAIT) and for clock (φ) output. The port 6 pin configuration is shown in figure 7.2. See table 7.4 for the selection of the pin functions.
Bit 7 is reserved. It is fixed at 1, and cannot be modified. — P6 DDR P6 DDR P6 DDR P6 DDR P6 DDR P6 DDR P6 DDR Initial value Read/Write — Reserved bit Port 6 data direction 6 to 0 These bits select input or output for port 6 pins •...
Table 7.5 Port 6 Pin Functions in Modes 1 to 4 Pin Functions and Selection Method /φ Bit PSTOP in MSTCRH selects the pin function. PSTOP φ output Pin function input Functions as LWR regardless of the setting of bit P6 LWR output Pin function Functions as HWR regardless of the setting of bit P6...
Port 7 7.4.1 Overview Port 7 is an 8-bit input port that is also used for analog input to the A/D converter and analog output from the D/A converter. The pin functions are the same in all operating modes. Figure 7.3 shows the pin configuration of port 7.
CS output, IRQ to IRQ input, and A/D converter ADTRG input. Figure 7.4 shows the pin configuration of port 8. In the H8/3008, port 8 can provide CS to CS output, IRQ to IRQ input, and ADTRG input. See table 7.8 for the selection of pin functions in expanded modes.
CS output, while CS to CS In the H8/3008, following a reset P8 are input ports. P8DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P8DDR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode P8DDR retains its previous setting.
Bits 7 to 5 are reserved. They are fixed at 1, and cannot be modified. — — — Initial value Read/Write — — — Reserved bits Port 8 data 4 to 0 These bits store data for port 8 pins P8DR is initialized to H'E0 by a reset and in hardware standby mode.
Table 7.8 Port 8 Pin Functions in Modes 1 to 4 Pin Functions and Selection Method Bit P8 DDR selects the pin function as follows. Pin function input output /IRQ Bit P8 DDR selects the pin function as follows ADTRG Pin function input output...
Port 9 7.6.1 Overview Port 9 is a 6-bit input/output port that is also used for input and output (TxD , TxD , RxD , RxD ) by serial communication interface channels 0 and 1 (SCI0 and SCI1), and for IRQ , SCK and IRQ input.
Port 9 Data Direction Register (P9DDR): P9DDR is an 8-bit write-only register that can select input or output for each pin in port 9. Bits 7 and 6 are reserved. They are fixed at 1, and cannot be modified. — —...
Table 7.10 Port 9 Pin Functions Pin Functions and Selection Method /SCK /IRQ Bit C/A in SMR of SCI1, bits CKE0 and CKE1 in SCR, and bit P9 select the pin function as follows. CKE1 — CKE0 — — — —...
Pin Functions and Selection Method /TxD Bit TE in SCR of SCI1, bit SMIF in SCMR, and bit P9 DDR select the pin function as follows. SMIF — — — Pin function input output output TxD output* Note: * Functions as the TxD output pin, but there are two states: one in which the pin is driven, and another in which the pin is at high- impedance.
Port A pins Pin functions in modes 1 and 2 PA (input/output)/TP (output)/TIOCB (input/output) PA /TP /TIOCB /A PA /TP /TIOCA /A PA (input/output)/TP (output)/TIOCA (input/output) PA (input/output)/TP (output)/TIOCB (input/output) PA /TP /TIOCB /A PA /TP /TIOCA /A PA (input/output)/TP (output)/TIOCA (input/output) Port A PA /TP /TIOCB /TCLKD PA (input/output)/TP (output)/TIOCB (input/output)/TCLKD (input)
PA DDR PA DDR PA DDR PA DDR PA DDR PA DDR PA DDR PA DDR Initial value Modes 3 and 4 Read/Write — Modes Initial value 1 and 2 Read/Write Port A data direction 7 to 0 These bits select input or output for port A pins The pin functions that can be selected for pins PA to PA differ between modes 1 and 2, and...
Table 7.12 Port A Pin Functions (Modes 1 and 2) Pin Functions and Selection Method Bit PWM2 in TMDR, bits IOB2 to IOB0 in TIOR2, bit NDER7 in NDERA, and bit TIOCB PA 7 DDR select the pin function as follows. 16-bit timer channel 2 settings (1) in table below...
Pin Functions and Selection Method Bit PWM1 in TMDR, bits IOB2 to IOB0 in TIOR1, bit NDER5 in NDERA, and bit TIOCB DDR select the pin function as follows. 16-bit timer channel 1 settings (1) in table below (2) in table below —...
Table 7.13 Port A Pin Functions (Modes 3 and 4) Pin Functions and Selection Method Always used as A output. Pin function output Bit PWM2 in TMDR, bits IOA2 to IOA0 in TIOR2, bit NDER6 in NDERA, bit A21E in TIOCA BRCR, and bit PA DDR select the pin function as follows.
Pin Functions and Selection Method Bit PWM1 in TMDR, bits IOB2 to IOB0 in TIOR1, bit NDER5 in NDERA, bit A22E in TIOCB BRCR, and bit PA DDR select the pin function as follows. A22E 16-bit timer channel 1 settings (1) in table below (2) in table below —...
Table 7.14 Port A Pin Functions (Modes 1 to 4) Pin Functions and Selection Method Bit PWM0 in TMDR, bits IOB2 to IOB0 in TIOR0, bits TPSC2 to TPSC0 in 16TCR2 to TIOCB 16TCR0 of the 16-bit timer, bits CKS2 to CKS0 in 8TCR2 of the 8-bit timer, bit TCLKD NDER3 in NDERA, and bit PA DDR select the pin function as follows.
Pin Functions and Selection Method Bit PWM0 in TMDR, bits IOA2 to IOA0 in TIOR0, bits TPSC2 to TPSC0 in 16TCR2 to TIOCA 16TCR0 of the 16-bit timer, bits CKS2 to CKS0 in 8TCR0 of the 8-bit timer, bit TCLKC NDER2 in NDERA, and bit PA DDR select the pin function as follows.
Pin Functions and Selection Method Bit MDF in TMDR, bits TPSC2 to TPSC0 in 16TCR2 to 16TCR0 of the 16-bit timer, TCLKB bits CKS2 to CKS0 in 8TCR3 of the 8-bit timer, bit NDER1 in NDERA, and bit DDR select the pin function as follows. NDER1 —...
Port B 7.8.1 Overview Port B is an 8-bit input/output port that is also used for output (TP to TP ) from the programmable timing pattern controller (TPC), input/output (TMIO , TMO , TMIO , TMO ) by the 8-bit timer, and CS to CS output.
7.8.2 Register Descriptions Table 7.15 summarizes the registers of port B. Table 7.15 Port B Registers Address* Name Abbreviation Initial Value H'EE00A Port B data direction register PBDDR H'00 H'FFFDA Port B data register PBDR H'00 Note: * Lower 20 bits of the address in advanced mode. Port B Data Direction Register (PBDDR): PBDDR is an 8-bit write-only register that can select input or output for each pin in port B.
Port B Data Register (PBDR): PBDR is an 8-bit readable/writable register that stores output data for pins port B. When port B functions as an output port, the value of this register is output. When a bit in PBDDR is set to 1, if port B is read the value of the corresponding PBDR bit is returned. When a bit in PBDDR is cleared to 0, if port B is read the corresponding pin logic level is read.
Table 7.16 Port B Pin Functions (Modes 1 to 4) Pin Functions and Selection Method Bit NDER15 in NDERB and bit PB DDR select the pin function as follows. NDER15 — Pin function input output output Bit NDER14 in NDERB and bit PB DDR select the pin function as follows.
Pin Functions and Selection Method Bits OIS3/2 and OS1/0 in 8TCSR2, bit CS5E in CSCR, bit NDER10 in NDERB, and bit PB DDR select the pin function as follows. OIS3/2 and All 0 Not all 0 OS1/0 CS5E — — —...
Section 8 16-Bit Timer Overview The H8/3008 has built-in 16-bit timer module with three 16-bit counter channels. 8.1.1 Features 16-bit timer features are listed below. • Capability to process up to 6 pulse outputs or 6 pulse inputs • Six general registers (GRs, two per channel) with independently-assignable output compare or input capture functions •...
• Output triggering of programmable timing pattern controller (TPC) Compare match/input capture signals from channels 0 to 2 can be used as TPC output triggers. Table 8.1 summarizes the 16-bit timer functions. Table 8.1 16-bit timer Functions Item Channel 0 Channel 1 Channel 2 Internal clocks: φ, φ/2, φ/4, φ/8...
8.1.2 Block Diagrams 16-bit timer Block Diagram (Overall): Figure 8.1 is a block diagram of the 16-bit timer. IMIA0 to IMIA2 TCLKA to TCLKD Clock selector IMIB0 to IMIB2 φ, φ/2, φ/4, φ/8 OVI0 to OVI2 Control logic TIOCA to TIOCA TIOCB to TIOCB TSTR...
Block Diagram of Channels 0 and 1: 16-bit timer channels 0 and 1 are functionally identical. Both have the structure shown in figure 8.2. TCLKA to TCLKD TIOCA Clock selector TIOCB φ, φ/2, φ/4, φ/8 Control logic IMIA0 Comparator IMIB0 OVI0 Module data bus Legend:...
Block Diagram of Channel 2: Figure 8.3 is a block diagram of channel 2 TCLKA to TCLKD TIOCA Clock selector TIOCB φ, φ/2, φ/4, φ/8 Control logic IMIA2 Comparator IMIB2 OVI2 Module data bus Legend: 16TCNT2: Timer counter 2 (16 bits) GRA2, GRB2: General registers A2 and B2 (input capture/output compare registers) (16 bits ×...
Bit 1—Counter Start 1 (STR1): Starts and stops timer counter 1 (16TCNT1). Bit 1 STR1 Description 16TCNT1 is halted (Initial value) 16TCNT1 is counting Bit 0—Counter Start 0 (STR0): Starts and stops timer counter 0 (16TCNT0). Bit 0 STR0 Description 16TCNT0 is halted (Initial value) 16TCNT0 is counting...
Bit 1—Timer Sync 1 (SYNC1): Selects whether channel 1 operates independently or synchronously. Bit 1 SYNC1 Description Channel 1’s timer counter (16TCNT1) operates independently (Initial value) 16TCNT1 is preset and cleared independently of other channels Channel 1 operates synchronously 16TCNT1 can be synchronously preset and cleared Bit 0—Timer Sync 0 (SYNC0): Selects whether channel 0 operates independently or synchronously.
Bit 7—Reserved: This bit cannot be modified and is always read as 1. Bit 6—Phase Counting Mode Flag (MDF): Selects whether channel 2 operates normally or in phase counting mode. Bit 6 Description Channel 2 operates normally (Initial value) Channel 2 operates in phase counting mode When MDF is set to 1 to select phase counting mode, 16TCNT2 operates as an up/down-counter and pins TCLKA and TCLKB become counter clock input pins.
Bit 2—PWM Mode 2 (PWM2): Selects whether channel 2 operates normally or in PWM mode. Bit 2 PWM2 Description Channel 2 operates normally (Initial value) Channel 2 operates in PWM mode When bit PWM2 is set to 1 to select PWM mode, pin TIOCA becomes a PWM output pin.
8.2.4 Timer Interrupt Status Register A (TISRA) TISRA is an 8-bit readable/writable register that indicates GRA compare match or input capture and enables or disables GRA compare match and input capture interrupt requests. — IMIEA2 IMIEA1 IMIEA0 — IMFA2 IMFA1 IMFA0 Initial value Read/Write...
Bit 5—Input Capture/Compare Match Interrupt Enable A1 (IMIEA1): Enables or disables the interrupt requested by the IMFA1 flag when IMFA1 is set to 1. Bit 5 IMIEA1 Description IMIA1 interrupt requested by IMFA1 flag is disabled (Initial value) IMIA1 interrupt requested by IMFA1 flag is enabled Bit 4—Input Capture/Compare Match Interrupt Enable A0 (IMIEA0): Enables or disables the interrupt requested by the IMFA0 flag when IMFA0 is set to 1.
Bit 1—Input Capture/Compare Match Flag A1 (IMFA1): This status flag indicates GRA1 compare match or input capture events. Bit 1 IMFA1 Description [Clearing condition] (Initial value) Read IMFA1 flag when IMFA1 =1, then write 0 in IMFA1 flag [Setting conditions] •...
8.2.5 Timer Interrupt Status Register B (TISRB) TISRB is an 8-bit readable/writable register that indicates GRB compare match or input capture and enables or disables GRB compare match and input capture interrupt requests. — IMIEB2 IMIEB1 IMIEB0 — IMFB2 IMFB1 IMFB0 Initial value Read/Write...
Bit 5—Input Capture/Compare Match Interrupt Enable B1 (IMIEB1): Enables or disables the interrupt requested by the IMFB1 when IMFB1 flag is set to 1. Bit 5 IMIEB1 Description IMIB1 interrupt requested by IMFB1 flag is disabled (Initial value) IMIB1 interrupt requested by IMFB1 flag is enabled Bit 4—Input Capture/Compare Match Interrupt Enable B0 (IMIEB0): Enables or disables the interrupt requested by the IMFB0 when IMFB0 flag is set to 1.
Bit 1—Input Capture/Compare Match Flag B1 (IMFB1): This status flag indicates GRB1 compare match or input capture events. Bit 1 IMFB1 Description [Clearing condition] (Initial value) Read IMFB1 flag when IMFB1 =1, then write 0 in IMFB1 flag [Setting conditions] •...
8.2.6 Timer Interrupt Status Register C (TISRC) TISRC is an 8-bit readable/writable register that indicates 16TCNT overflow or underflow and enables or disables overflow interrupt requests. — OVIE2 OVIE1 OVIE0 — OVF2 OVF1 OVF0 Initial value Read/Write — — R/(W)* R/(W)* R/(W)* Overflow flags 2 to 0...
Bit 4—Overflow Interrupt Enable 0 (OVIE0): Enables or disables the interrupt requested by the OVF0 when OVF0 flag is set to 1. Bit 4 OVIE0 Description OVI0 interrupt requested by OVF0 flag is disabled (Initial value) OVI0 interrupt requested by OVF0 flag is enabled Bit 3—Reserved: This bit cannot be modified and is always read as 1.
8.2.7 Timer Counters (16TCNT) 16TCNT is a 16-bit counter. The 16-bit timer has three 16TCNTs, one for each channel. Channel Abbreviation Function 16TCNT0 Up-counter 16TCNT1 16TCNT2 Phase counting mode: up/down-counter Other modes: up-counter Initial value Read/Write Each 16TCNT is a 16-bit readable/writable register that counts pulse inputs from a clock source. The clock source is selected by bits TPSC2 to TPSC0 in 16TCR.
8.2.8 General Registers (GRA, GRB) The general registers are 16-bit registers. The 16-bit timer has 6 general registers, two in each channel. Channel Abbreviation Function GRA0, GRB0 Output compare/input capture register GRA1, GRB1 GRA2, GRB2 Initial value Read/Write A general register is a 16-bit readable/writable register that can function as either an output compare register or an input capture register.
8.2.9 Timer Control Registers (16TCR) 16TCR is an 8-bit register. The 16-bit timer has three 16TCRs, one in each channel. Channel Abbreviation Function 16TCR0 16TCR controls the timer counter. The 16TCRs in all channels are functionally identical. When phase counting 16TCR1 mode is selected in channel 2, the settings of bits CKEG1 and CKEG0 and TPSC2 to TPSC0 in 16TCR2 are ignored.
Bits 6 and 5—Counter Clear 1 and 0 (CCLR1, CCLR0): These bits select how 16TCNT is cleared. Bit 6 Bit 5 CCLR1 CCLR0 Description 16TCNT is not cleared (Initial value) 16TCNT is cleared by GRA compare match or input capture* 16TCNT is cleared by GRB compare match or input capture* Synchronous clear: 16TCNT is cleared in synchronization with other synchronized timers*...
When bit TPSC2 is cleared to 0 an internal clock source is selected, and the timer counts only falling edges. When bit TPSC2 is set to 1 an external clock source is selected, and the timer counts the edges selected by bits CKEG1 and CKEG0. When channel 2 is set to phase counting mode (MDF = 1 in TMDR), the settings of bits TPSC2 to TPSC0 in 16TCR2 are ignored.
Bits 6 to 4—I/O Control B2 to B0 (IOB2 to IOB0): These bits select the GRB function. Bit 6 Bit 5 Bit 4 IOB2 IOB1 IOB0 Function GRB is an output No output at compare match (Initial value) compare register 0 output at GRB compare match* 1 output at GRB compare match* Output toggles at GRB compare match...
8.2.11 Timer Output Level Setting Register C (TOLR) TOLR is an 8-bit write-only register that selects the timer output level for channels 0 to 2. — — TOB2 TOA2 TOB1 TOA1 TOB0 TOA0 Initial value Read/Write — — Output level setting A2 to A0, B2 to B0 These bits set the levels of the timer outputs (TIOCA to TIOCA...
Bit 3—Output Level Setting B1 (TOB1): Sets the value of timer output TIOCB Bit 3 TOB1 Description TIOCB is 0 (Initial value) TIOCB is 1 Bit 2—Output Level Setting A1 (TOA1): Sets the value of timer output TIOCA Bit 2 TOA1 Description TIOCA...
CPU Interface 8.3.1 16-Bit Accessible Registers The timer counters (16TCNTs), general registers A and B (GRAs and GRBs) are 16-bit registers, and are linked to the CPU by an internal 16-bit data bus. These registers can be written or read a word at a time, or a byte at a time.
On-chip data bus Module Bus interface data bus 16TCNTH 16TCNTL Figure 8.6 Access to Timer Counter H (CPU Writes to 16TCNTH, Upper Byte) On-chip data bus Module Bus interface data bus 16TCNTH 16TCNTL Figure 8.7 Access to Timer Counter L (CPU Writes to 16TCNTL, Lower Byte) On-chip data bus Module Bus interface...
On-chip data bus Module Bus interface data bus 16TCNTH 16TCNTL Figure 8.9 Access to Timer Counter L (CPU Reads 16TCNTL, Lower Byte) 8.3.2 8-Bit Accessible Registers The registers other than the timer counters and general registers are 8-bit registers. These registers are linked to the CPU by an internal 8-bit data bus.
Operation 8.4.1 Overview A summary of operations in the various modes is given below. Normal Operation: Each channel has a timer counter and general registers. The timer counter counts up, and can operate as a free-running counter, periodic counter, or external event counter. GRA and GRB can be used for input capture or output compare.
Counter setup Select counter clock Count operation Free-running counting Periodic counting Select counter clear source Select output compare register function Set period Start counter Start counter Periodic counter Free-running counter Figure 8.12 Counter Setup Procedure (Example) 1. Set bits TPSC2 to TPSC0 in 16TCR to select the counter clock source. If an external clock source is selected, set bits CKEG1 and CKEG0 in 16TCR to select the desired edge(s) of the external clock signal.
• Free-running and periodic counter operation A reset leaves the counters (16TCNTs) in 16-bit timer channels 0 to 2 all set as free-running counters. A free-running counter starts counting up when the corresponding bit in TSTR is set to 1. When the count overflows from H'FFFF to H'0000, the OVF flag is set to 1 in TISRC. After the overflow, the counter continues counting up from H'0000.
• 16TCNT count timing Internal clock source Bits TPSC2 to TPSC0 in 16TCR select the system clock (φ) or one of three internal clock sources obtained by prescaling the system clock (φ/2, φ/4, φ/8). Figure 8.15 shows the timing. φ...
Waveform Output by Compare Match: In 16-bit timer channels 0, 1 compare match A or B can cause the output at the TIOCA or TIOCB pin to go to 0, go to 1, or toggle. In channel 2 the output can only go to 0 or go to 1.
• Examples of waveform output Figure 8.18 shows examples of 0 and 1 output. 16TCNT operates as a free-running counter, 0 output is selected for compare match A, and 1 output is selected for compare match B. When the pin is already at the selected output level, the pin level does not change. 16TCNT value H'FFFF H'0000...
• Output compare output timing The compare match signal is generated in the last state in which 16TCNT and the general register match (when 16TCNT changes from the matching value to the next value). When the compare match signal is generated, the output value selected in TIOR is output at the output compare pin (TIOCA or TIOCB).
• Sample setup procedure for input capture Figure 8.21 shows a sample procedure for setting up input capture. Input selection Set TIOR to select the input capture function of a general register and the rising edge, falling edge, or both edges of the input capture signal. Clear the DDR bit to 0 before making these TIOR settings.
• Input capture signal timing Input capture on the rising edge, falling edge, or both edges can be selected by settings in TIOR. Figure 8.23 shows the timing when the rising edge is selected. The pulse width of the input capture signal must be at least 1.5 system clocks for single-edge capture, and 2.5 system clocks for capture of both edges.
Setup for synchronization Select synchronization Synchronous preset Synchronous clear Clearing synchronized to this channel? Write to 16TCNT Select counter clear source Select counter clear source Start counter Start counter Synchronous preset Counter clear Synchronous clear Set the SYNC bits to 1 in TSNC for the channels to be synchronized. When a value is written in 16TCNT in one of the synchronized channels, the same value is simultaneously written in 16TCNT in the other channels.
Value of 16TCNT0 to 16TCNT2 Cleared by compare match with GRB0 GRB0 GRB1 GRA0 GRB2 GRA1 GRA2 H'0000 TIOCA TIOCA TIOCA Figure 8.25 Synchronization (Example) 8.4.4 PWM Mode In PWM mode GRA and GRB are paired and a PWM waveform is output from the TIOCA pin. GRA specifies the time at which the PWM output changes to 1.
Sample Setup Procedure for PWM Mode: Figure 8.26 shows a sample procedure for setting up PWM mode. PWM mode Set bits TPSC2 to TPSC0 in 16TCR to select the counter clock source. If an external clock source is selected, set bits CKEG1 and CKEG0 in 16TCR to select the desired edge(s) of the Select counter clock...
Examples of PWM Mode: Figure 8.27 shows examples of operation in PWM mode. In PWM mode TIOCA becomes an output pin. The output goes to 1 at compare match with GRA, and to 0 at compare match with GRB. In the examples shown, 16TCNT is cleared by compare match with GRA or GRB. Synchronized operation and free-running counting are also possible.
Figure 8.28 shows examples of the output of PWM waveforms with duty cycles of 0% and 100%. If the counter is cleared by compare match with GRB, and GRA is set to a higher value than GRB, the duty cycle is 0%. If the counter is cleared by compare match with GRA, and GRB is set to a higher value than GRA, the duty cycle is 100%.
8.4.5 Phase Counting Mode In phase counting mode the phase difference between two external clock inputs (at the TCLKA and TCLKB pins) is detected, and 16TCNT2 counts up or down accordingly. In phase counting mode, the TCLKA and TCLKB pins automatically function as external clock input pins and 16TCNT2 becomes an up/down-counter, regardless of the settings of bits TPSC2 to TPSC0, CKEG1, and CKEG0 in 16TCR2.
Example of Phase Counting Mode: Figure 8.30 shows an example of operations in phase counting mode. Table 8.5 lists the up-counting and down-counting conditions for 16TCNT2. In phase counting mode both the rising and falling edges of TCLKA and TCLKB are counted. The phase difference between TCLKA and TCLKB must be at least 1.5 states, the phase overlap must also be at least 1.5 states, and the pulse width must be at least 2.5 states.
8.4.6 16-Bit Timer Output Timing The initial value of 16-bit timer output when a timer count operation begins can be specified arbitrarily by making a setting in TOLR. Figure 8.32 shows the timing for setting the initial value with TOLR. Only write to TOLR when the corresponding bit in TSTR is cleared to 0.
Interrupts The 16-bit timer has two types of interrupts: input capture/compare match interrupts, and overflow interrupts. 8.5.1 Setting of Status Flags Timing of Setting of IMFA and IMFB at Compare Match: IMFA and IMFB are set to 1 by a compare match signal generated when 16TCNT matches a general register (GR).
Timing of Setting of IMFA and IMFB by Input Capture: IMFA and IMFB are set to 1 by an input capture signal. The 16TCNT contents are simultaneously transferred to the corresponding general register. Figure 8.34 shows the timing. φ Input capture signal 16TCNT Figure 8.34 Timing of Setting of IMFA and IMFB by Input Capture...
Timing of Setting of Overflow Flag (OVF): OVF is set to 1 when 16TCNT overflows from H'FFFF to H'0000 or underflows from H'0000 to H'FFFF. Figure 8.35 shows the timing. φ 16TCNT Overflow signal Figure 8.35 Timing of Setting of OVF 8.5.2 Timing of Clearing of Status Flags If the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is...
8.5.3 Interrupt Sources Each 16-bit timer channel can generate a compare match/input capture A interrupt, a compare match/input capture B interrupt, and an overflow interrupt. In total there are nine interrupt sources of three kinds, all independently vectored. An interrupt is requested when the interrupt request flag are set to 1.
Usage Notes This section describes contention and other matters requiring special attention during 16-bit timer operations. Contention between 16TCNT Write and Clear: If a counter clear signal occurs in the T state of a 16TCNT write cycle, clearing of the counter takes priority and the write is not performed. See figure 8.37.
Contention between 16TCNT Word Write and Increment: If an increment pulse occurs in the state of a 16TCNT word write cycle, writing takes priority and 16TCNT is not incremented. Figure 8.38 shows the timing in this case. 16TCNT word write cycle φ...
Contention between 16TCNT Byte Write and Increment: If an increment pulse occurs in the or T state of a 16TCNT byte write cycle, writing takes priority and 16TCNT is not incremented. The byte data for which a write was not performed is not incremented, and retains its pre-write value.
Contention between General Register Write and Compare Match: If a compare match occurs in the T state of a general register write cycle, writing takes priority and the compare match signal is inhibited. See figure 8.40. General register write cycle φ...
Contention between 16TCNT Write and Overflow or Underflow: If an overflow occurs in the state of a 16TCNT write cycle, writing takes priority and the counter is not incremented. OVF set to 1.The same holds for underflow. See figure 8.41. 16TCNT write cycle φ...
Contention between General Register Read and Input Capture: If an input capture signal occurs during the T state of a general register read cycle, the value before input capture is read. See figure 8.42. General register read cycle φ Address bus GR address Internal read signal Input capture signal...
Contention between Counter Clearing by Input Capture and Counter Increment: If an input capture signal and counter increment signal occur simultaneously, the counter is cleared according to the input capture signal. The counter is not incremented by the increment signal. The value before the counter is cleared is transferred to the general register.
Contention between General Register Write and Input Capture: If an input capture signal occurs in the T state of a general register write cycle, input capture takes priority and the write to the general register is not performed. See figure 8.44. General register write cycle φ...
Note on Waveform Period Setting: When a counter is cleared by compare match, the counter is cleared in the last state at which the 16TCNT value matches the general register value, at the time when this value would normally be updated to the next count. The actual counter frequency is therefore given by the following formula: φ...
Section 9 8-Bit Timers Overview The H8/3008 has a built-in 8-bit timer module with four channels (TMR0, TMR1, TMR2, and TMR3), based on 8-bit counters. Each channel has an 8-bit timer counter (8TCNT) and two 8-bit time constant registers (TCORA and TCORB) that are constantly compared with the 8TCNT value to detect compare match events.
• Twelve interrupt sources There are twelve interrupt sources: four compare match sources, four compare match/input capture sources, four overflow sources. Two of the compare match sources and two of the combined compare match/input capture sources each have an independent interrupt vector. The remaining compare match interrupts, combined compare match/input capture interrupts, and overflow interrupts have one interrupt vector for two sources.
9.1.2 Block Diagram The 8-bit timers are divided into two groups of two channels each: group 0 comprising channels 0 and 1, and group 1 comprising channels 2 and 3. Figure 9.1 shows a block diagram of 8-bit timer group 0. External clock Internal clock sources...
Register Descriptions 9.2.1 Timer Counters (8TCNT) 8TCNT0 8TCNT1 Initial value Read/Write 8TCNT2 8TCNT3 Initial value Read/Write The timer counters (8TCNT) are 8-bit readable/writable up-counters that increment on pulses generated from an internal or external clock source. The clock source is selected by clock select bits 2 to 0 (CKS2 to CKS0) in the timer control register (8TCR).
9.2.2 Time Constant Registers A (TCORA) TCORA0 to TCORA3 are 8-bit readable/writable registers. TCORA0 TCORA1 Initial value Read/Write TCORA2 TCORA3 Initial value Read/Write The TCORA0 and TCORA1 pair, and the TCORA2 and TCORA3 pair, can each be accessed as a 16-bit register by word access.
9.2.3 Time Constant Registers B (TCORB) TCORB0 TCORB1 Initial value Read/Write TCORB2 TCORB3 Initial value Read/Write TCORB0 to TCORB3 are 8-bit readable/writable registers. The TCORB0 and TCORB1 pair, and the TCORB2 and TCORB3 pair, can each be accessed as a 16-bit register by word access. The TCORB value is constantly compared with the 8TCNT value.
9.2.4 Timer Control Register (8TCR) CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Initial value Read/Write 8TCR is an 8-bit readable/writable register that selects the 8TCNT input clock, gives the 8TCNT clearing specification, and enables interrupt requests. 8TCR is initialized to H'00 by a reset and in standby mode. For the timing, see section 9.4, Operation.
Bits 4 and 3—Counter Clear 1 and 0 (CCLR1, CCLR0): These bits specify the 8TCNT clearing source. Compare match A or B, or input capture B, can be selected as the clearing source. Bit 4 Bit 3 CCLR1 CCLR0 Description Clearing is disabled (Initial value) Cleared by compare match A...
Bit 2 Bit 1 Bit 0 CSK2 CSK1 CSK0 Description Clock input disabled (Initial value) Internal clock, counted on falling edge of φ/8 Internal clock, counted on falling edge of φ/64 Internal clock, counted on falling edge of φ/8192 Channel 0 (16-bit count mode): Count on 8TCNT1 overflow signal* Channel 1 (compare match count mode): Count on 8TCNT0 compare match A*...
9.2.5 Timer Control/Status Registers (8TCSR) 8TCSR0 CMFB CMFA OIS3 OIS2 ADTE Initial value Read/Write R/(W)* R/(W)* R/(W)* 8TCSR2 CMFB CMFA — OIS3 OIS2 Initial value Read/Write R/(W)* R/(W)* R/(W)* — 8TCSR1, 8TCSR3 CMFB CMFA OIS3 OIS2 Initial value Read/Write R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
Bit 7—Compare Match/Input Capture Flag B (CMFB): Status flag that indicates the occurrence of a TCORB compare match or input capture. Bit 7 CMFB Description [Clearing condition] (Initial value) Read CMFB when CMFB = 1, then write 0 in CMFB [Setting conditions] •...
Bit 4—A/D Trigger Enable (ADTE) (In 8TCSR0): In combination with TRGE in the A/D control register (ADCR), enables or disables A/D converter start requests by compare match A or an external trigger. Bit 4 TRGE* ADTE Description A/D converter start requests by compare match A or external trigger pin (ADTRG) input are disabled (Initial value) A/D converter start requests by compare match A or external trigger pin...
Table 9.3 Operation of Channels 0 and 1 when Bit ICE is Set to 1 in 8TCSR1 Register Register Timer Output Register Function Status Flag Change Capture Input Interrupt Request TCORA0 Compare match CMFA changed from 0 output CMIA0 interrupt request operation to 1 in 8TCSR0 by controllable...
Bits 3 and 2—Output/Input Capture Edge Select B3 and B2 (OIS3, OIS2): In combination with the ICE bit in 8TCSR1 (8TCSR3), these bits select the compare match B output level or the input capture input detected edge. The function of TCORB1 (TCORB3) depends on the setting of bit 4 of 8TCSR1 (8TCSR3). ICE Bit in 8TCSR1 Bit 3...
CPU Interface 9.3.1 8-Bit Registers 8TCNT, TCORA, TCORB, 8TCR, and 8TCSR are 8-bit registers. These registers are connected to the CPU by an internal 16-bit data bus and can be read and written a word at a time or a byte at a time.
Internal data bus Module data bus interface 8TCNTH0 8TCNTL1 Figure 9.5 8TCNT1 Access Operation (CPU Writes to 8TCNT1, Lower Byte) Internal data bus Module data bus interface 8TCNT0 8TCNT1 Figure 9.6 8TCNT0 Access Operation (CPU Reads 8TCNT0, Upper Byte) Internal data bus Module data bus interface 8TCNT0 8TCNT1...
Operation 9.4.1 8TCNT Count Timing 8TCNT is incremented by input clock pulses (either internal or external). Internal Clock: Three different internal clock signals (φ/8, φ/64, or φ/8192) divided from the system clock (φ) can be selected, by setting bits CKS2 to CKS0 in 8TCR. Figure 9.8 shows the count timing.
φ External clock input 8TCNT input clock N–1 8TCNT Figure 9.9 Count Timing for External Clock Input (Both-Edge Detection) 9.4.2 Compare Match Timing Timer Output Timing: When compare match A or B occurs, the timer output is as specified by the OIS3, OIS2, OS1, and OS0 bits in 8TCSR (unchanged, 0 output, 1 output, or toggle output).
Clear by Compare Match: Depending on the setting of the CCLR1 and CCLR0 bits in 8TCR, 8TCNT can be cleared when compare match A or B occurs, Figure 9.11 shows the timing of this operation. φ Compare match signal 8TCNT H'00 Figure 9.11 Timing of Clear by Compare Match Clear by Input Capture: Depending on the setting of the CCLR1 and CCLR0 bits in 8TCR,...
φ Input capture input Input capture signal 8TCNT TCORB Figure 9.13 Timing of Input Capture Input Signal 9.4.4 Timing of Status Flag Setting Timing of CMFA/CMFB Flag Setting when Compare Match Occurs: The CMFA and CMFB flags in 8TCSR are set to 1 by the compare match signal output when the TCORA or TCORB and 8TCNT values match.
φ 8TCNT TCORB Input capture signal CMFB Figure 9.15 CMFB Flag Setting Timing when Input Capture Occurs Timing of Overflow Flag (OVF) Setting: The OVF flag in 8TCSR is set to 1 by the overflow signal generated when 8TCNT overflows (from H'FF to H'00). Figure 9.16 shows the timing in this case.
16-Bit Count Mode • Channels 0 and 1: When bits CKS2 to CKS0 are set to (100) in 8TCR0, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. ...
Setting when Input Capture Occurs • The CMFB flag is set to 1 in 8TCSR2 and 8TCSR3 when the ICE bit is 1 in TCSR3 and input capture occurs. • TMIO pin input capture input signal edge detection is selected by bits OIS3 and OIS2 in 8TCSR2.
9.4.6 Input Capture Setting The 8TCNT value can be transferred to TCORB on detection of an input edge on the input capture/output compare pin (TMIO or TMIO ). Rising edge, falling edge, or both edge detection can be selected. In 16-bit count mode, 16-bit input capture can be used. Setting Input Capture Operation in 8-Bit Timer Mode (Normal Operation) •...
Interrupt 9.5.1 Interrupt Sources The 8-bit timer unit can generate three types of interrupt: compare match A and B (CMIA and CMIB) and overflow (TOVI). Table 9.5 shows the interrupt sources and their priority order. Each interrupt source is enabled or disabled by the corresponding interrupt enable bit in 8TCR. A separate interrupt request signal is sent to the interrupt controller by each interrupt source.
9.5.2 A/D Converter Activation The A/D converter can only be activated by channel 0 compare match A. If the ADTE bit setting is 1 when the CMFA flag in 8TCSR0 is set to 1 by generation of channel 0 compare match A, an A/D conversion start request will be issued to the A/D converter. If the TRGE bit in ADCR is 1 at this time, the A/D converter will be started.
Usage Notes Note that the following kinds of contention can occur in 8-bit timer operation. 9.7.1 Contention between 8TCNT Write and Clear If a timer counter clear signal occurs in the T state of a 8TCNT write cycle, clearing of the counter takes priority and the write is not performed.
9.7.2 Contention between 8TCNT Write and Increment If an increment pulse occurs in the T state of a 8TCNT write cycle, writing takes priority and 8TCNT is not incremented. Figure 9.19 shows the timing in this case. 8TCNT write cycle φ...
9.7.3 Contention between TCOR Write and Compare Match If a compare match occurs in the T state of a TCOR write cycle, writing takes priority and the compare match signal is inhibited. Figure 9.20 shows the timing in this case. TCOR write cycle φ...
9.7.4 Contention between TCOR Read and Input Capture If an input capture signal occurs in the T state of a TCOR read cycle, the value before input capture is read. Figure 9.21 shows the timing in this case. TCORB read cycle φ...
9.7.5 Contention between Counter Clearing by Input Capture and Counter Increment If an input capture signal and counter increment signal occur simultaneously, counter clearing by the input capture signal takes priority and the counter is not incremented. The value before the counter is cleared is transferred to TCORB.
9.7.6 Contention between TCOR Write and Input Capture If an input capture signal occurs in the T state of a TCOR write cycle, input capture takes priority and the write to TCOR is not performed. Figure 9.23 shows the timing in this case. TCOR write cycle φ...
9.7.7 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode (Cascaded Connection) If an increment pulse occurs in the T state of an 8TCNT byte write cycle in 16-bit count mode, the counter write takes priority and the byte data for which the write was performed is not incremented.
9.7.8 Contention between Compare Matches A and B If compare matches A and B occur at the same time, the 8-bit timer operates according to the relative priority of the output states set for compare match A and compare match B, as shown in Table 9.7.
Table 9.8 Internal Clock Switchover and 8TCNT Operation CKS1 and CKS0 Write Timing 8TCNT Operation High → high switchover* Old clock source New clock source 8TCNT clock 8TCNT CKS bits rewritten High → low switchover* Old clock source New clock source 8TCNT clock 8TCNT...
CKS1 and CKS0 Write Timing 8TCNT Operation Low → low switchover* Old clock source New clock source 8TCNT clock 8TCNT CKS bits rewritten Notes: 1. Including switchovers from the high level to the halted state, and from the halted state to the high level.
10.1 Overview The H8/3008 has a built-in programmable timing pattern controller (TPC) that provides pulse outputs by using the 16-bit timer as a time base. The TPC pulse outputs are divided into 4-bit groups (group 3 to group 0) that can operate simultaneously and independently.
10.1.2 Block Diagram Figure 10.1 shows a block diagram of the TPC. 16-bit timer compare match signals PADDR PBDDR NDERA NDERB Control logic TPMR TPCR Internal data bus Pulse output pins, group 3 PBDR NDRB Pulse output pins, group 2 Pulse output pins, group 1 PADR...
10.1.4 Register Configuration Table 10.2 summarizes the TPC registers. Table 10.2 TPC Registers Address* Name Abbreviation Initial Value H'EE009 Port A data direction register PADDR H'00 H'FFFD9 Port A data register PADR R/(W)* H'00 H'EE00A Port B data direction register PBDDR H'00 H'FFFDA...
10.2 Register Descriptions 10.2.1 Port A Data Direction Register (PADDR) PADDR is an 8-bit write-only register that selects input or output for each pin in port A. PA DDR PA DDR PA DDR PA DDR PA DDR PA DDR PA DDR PA DDR Initial value Read/Write...
10.2.3 Port B Data Direction Register (PBDDR) PBDDR is an 8-bit write-only register that selects input or output for each pin in port B. PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR Initial value Read/Write Port B data direction 7 to 0...
10.2.5 Next Data Register A (NDRA) NDRA is an 8-bit readable/writable register that stores the next output data for TPC output groups 1 and 0 (pins TP to TP ). During TPC output, when an 16-bit timer compare match event specified in TPCR occurs, NDRA contents are transferred to the corresponding bits in PADR.
Different Triggers for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered by different compare match events, the address of the upper 4 bits of NDRA (group 1) is H'FFFA5 and the address of the lower 4 bits (group 0) is H'FFFA7. Bits 3 to 0 of address H'FFFA5 and bits 7 to 4 of address H'FFFA7 are reserved bits that cannot be modified and always read 1.
10.2.6 Next Data Register B (NDRB) NDRB is an 8-bit readable/writable register that stores the next output data for TPC output groups 3 and 2 (pins TP to TP ). During TPC output, when an 16-bit timer compare match event specified in TPCR occurs, NDRB contents are transferred to the corresponding bits in PBDR.
Different Triggers for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered by different compare match events, the address of the upper 4 bits of NDRB (group 3) is H'FFFA4 and the address of the lower 4 bits (group 2) is H'FFFA6. Bits 3 to 0 of address H'FFFA4 and bits 7 to 4 of address H'FFFA6 are reserved bits that cannot be modified and always read 1.
10.2.7 Next Data Enable Register A (NDERA) NDERA is an 8-bit readable/writable register that enables or disables TPC output groups 1 and 0 to TP ) on a bit-by-bit basis. NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 Initial value Read/Write Next data enable 7 to 0 These bits enable or disable...
10.2.8 Next Data Enable Register B (NDERB) NDERB is an 8-bit readable/writable register that enables or disables TPC output groups 3 and 2 to TP ) on a bit-by-bit basis. NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial value Read/Write Next data enable 15 to 8 These bits enable or disable...
10.2.9 TPC Output Control Register (TPCR) TPCR is an 8-bit readable/writable register that selects output trigger signals for TPC outputs on a group-by-group basis. G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value Read/Write Group 3 compare match select 1 and 0 These bits select the compare match Group 2 compare...
Bits 5 and 4—Group 2 Compare Match Select 1 and 0 (G2CMS1, G2CMS0): These bits select the compare match event that triggers TPC output group 2 (TP to TP Bit 5 Bit 4 G2CMS1 G2CMS0 Description TPC output group 2 (TP to TP ) is triggered by compare match in 16-bit timer channel 0...
10.2.10 TPC Output Mode Register (TPMR) TPMR is an 8-bit readable/writable register that selects normal or non-overlapping TPC output for each group. — — — — G3NOV G2NOV G1NOV G0NOV Initial value Read/Write — — — — Reserved bits Group 3 non-overlap Selects non-overlapping TPC output for group 3 (TP to TP )
Bit 3—Group 3 Non-Overlap (G3NOV): Selects normal or non-overlapping TPC output for group 3 (TP to TP Bit 3 G3NOV Description Normal TPC output in group 3 (output values change at (Initial value) compare match A in the selected 16-bit timer channel) Non-overlapping TPC output in group 3 (independent 1 and 0 output at compare match A and B in the selected 16-bit timer channel) Bit 2—Group 2 Non-Overlap (G2NOV): Selects normal or non-overlapping TPC output for...
10.3 Operation 10.3.1 Overview When corresponding bits in PADDR or PBDDR and NDERA or NDERB are set to 1, TPC output is enabled. The TPC output initially consists of the corresponding PADR or PBDR contents. When a compare-match event selected in TPCR occurs, the corresponding NDRA or NDRB bit contents are transferred to PADR or PBDR to update the output values.
10.3.2 Output Timing If TPC output is enabled, NDRA/NDRB contents are transferred to PADR/PBDR and output when the selected compare match event occurs. Figure 10.3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. φ...
10.3.3 Normal TPC Output Sample Setup Procedure for Normal TPC Output: Figure 10.4 shows a sample procedure for setting up normal TPC output. Normal TPC output Set TIOR to make GRA an output compare Select GR functions register (with output inhibited). Set GRA value Set the TPC output trigger period.
Example of Normal TPC Output (Example of Five-Phase Pulse Output): Figure 10.5 shows an example in which the TPC is used for cyclic five-phase pulse output. TCNT value Compare match TCNT H'0000 Time NDRB PBDR The 16-bit timer channel to be used as the output trigger channel is set up so that GRA is an output compare register and the counter will be cleared by compare match A.
10.3.4 Non-Overlapping TPC Output Sample Setup Procedure for Non-Overlapping TPC Output: Figure 10.6 shows a sample procedure for setting up non-overlapping TPC output. Non-overlapping TPC output Select GR functions Set TIOR to make GRA and GRB output compare registers (with output inhibited). Set GR values Set the TPC output trigger period in GRB 16-bit timer...
Example of Non-Overlapping TPC Output (Example of Four-Phase Complementary Non- Overlapping Output): Figure 10.7 shows an example of the use of TPC output for four-phase complementary non-overlapping pulse output. TCNT value TCNT H'0000 Time NDRB PBDR Non-overlap margin The 16-bit timer channel to be used as the output trigger channel is set up so that GRA and GRB are output compare registers and the counter will be cleared by compare match B.
10.3.5 TPC Output Triggering by Input Capture TPC output can be triggered by 16-bit timer input capture as well as by compare match. If GRA functions as an input capture register in the 16-bit timer channel selected in TPCR, TPC output will be triggered by the input capture signal.
10.4 Usage Notes 10.4.1 Operation of TPC Output Pins to TP are multiplexed with 16-bit timer, address bus, and other pin functions. When 16-bit timer, or address bus output is enabled, the corresponding pins cannot be used for TPC output. The data transfer from NDR bits to DR bits takes place, however, regardless of the usage of the pin.
Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A. NDR contents should not be altered during the interval from compare match B to compare match A (the non-overlap margin). This can be accomplished by having the IMFA interrupt service routine write the next data in NDR.
As a watchdog timer, it generates a reset signal for the H8/3008 chip if a system crash allows the timer counter (TCNT) to overflow before being rewritten. In interval timer operation, an interval timer interrupt is requested at each TCNT overflow.
11.1.2 Block Diagram Figure 11.1 shows a block diagram of the WDT. Overflow Internal TCNT data bus Read/ Interrupt Interrupt signal write control (interval timer) control TCSR Internal clock sources φ/2 RSTCSR φ/32 φ/64 Reset Reset control Clock φ/128 (internal, external) Clock φ/256 selector...
11.2.2 Timer Control/Status Register (TCSR) TCSR is an 8-bit readable and writable register. Its functions include selecting the timer mode and clock source. WT/IT — — CKS2 CKS1 CKS0 Initial value Read/Write R/(W) — — Clock select These bits select the TCNT clock source Reserved bits Timer enable...
Bit 6—Timer Mode Select (WT/IT): Selects whether to use the WDT as a watchdog timer or interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request when TCNT overflows. If used as a watchdog timer, the WDT generates a reset signal when TCNT overflows.
Bit 7—Watchdog Timer Reset (WRST): During watchdog timer operation, this bit indicates that TCNT has overflowed and generated a reset signal. This reset signal resets the entire H8/3008 chip internally. If bit RSTOE is set to 1, this reset signal is also output (low) at the RESO pin to initialize external system devices.
Bit 6—Reset Output Enable (RSTOE): Enables or disables external output at the RESO pin of the reset signal generated if TCNT overflows during watchdog timer operation. Note that there is no RESO pin in the versions with on-chip flash memory. Bit 6 RSTOE Description Reset signal is not output externally...
Writing to RSTCSR: RSTCSR must be written by a word transfer instruction. It cannot be written by byte transfer instructions. Figure 11.3 shows the format of data written to RSTCSR. To write 0 in the WRST bit, the write data must have H'A5 in the upper byte and H'00 in the lower byte.
TCNT value (normally by writing H'00) before overflow occurs. If TCNT fails to be rewritten and overflows due to a system crash etc., the H8/3008 is internally reset for a duration of 518 states. The watchdog reset signal can be externally output from the RESO pin to reset external system devices.
11.3.2 Interval Timer Operation Figure 11.5 illustrates interval timer operation. To use the WDT as an interval timer, clear bit WT/IT to 0 and set bit TME to 1 in TCSR. An interval timer interrupt request is generated at each TCNT overflow.
1 when TCNT overflows and OVF is set to 1. At the same time an internal reset signal is generated for the entire H8/3008 chip. This internal reset signal clears OVF to 0, but the WRST bit remains set to 1. The reset routine must therefore clear the WRST bit.
11.4 Interrupts During interval timer operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. 11.5 Usage Notes Contention between TCNT Write and Increment: If a timer counter clock pulse is generated during the T state of a write cycle to TCNT, the write takes priority and the timer count is not incremented.
12.1 Overview The H8/3008 has a serial communication interface (SCI) with two independent channels. The two channels have identical functions. The SCI can communicate in both asynchronous and synchronous mode. It also has a multiprocessor communication function for serial communication among two or more processors.
• Full-duplex communication The transmitting and receiving sections are independent, so the SCI can transmit and receive simultaneously. The transmitting and receiving sections are both double-buffered, so serial data can be transmitted and received continuously. • The following settings can be made for the serial data to be transferred: ...
12.1.2 Block Diagram Figure 12.1 shows a block diagram of the SCI. Module data bus Internal data bus φ Baud rate φ/ 4 SCMR generator φ/16 Transmit/receive φ/64 control Parity generate Clock Parity check External clock T E I T X I R X I E R I Legend:...
12.1.3 Pin Configuration The SCI has serial pins for each channel as listed in table 12.1. Table 12.1 SCI Pins Channel Name Abbreviation Function Serial clock pin Input/output clock input/output Receive data pin Input receive data input Transmit data pin Output transmit data output Serial clock pin...
12.1.4 Register Configuration The SCI has internal registers as listed in table 12.2. These registers select asynchronous or synchronous mode, specify the data format and bit rate, control the transmitter and receiver sections, and specify switching between the serial communication interface and smart card interface.
12.2 Register Descriptions 12.2.1 Receive Shift Register (RSR) RSR is the register that receives serial data. — — — — — — — — Read/Write The SCI loads serial data input at the RxD pin into RSR in the order received, LSB (bit 0) first, thereby converting the data to parallel data.
12.2.3 Transmit Shift Register (TSR) TSR is the register that transmits serial data. — — — — — Read/Write — — — The SCI loads transmit data from TDR to TSR, then transmits the data serially from the TxD pin, LSB (bit 0) first.
12.2.5 Serial Mode Register (SMR) SMR is an 8-bit register that specifies the SCI's serial communication format and selects the clock source for the baud rate generator. STOP CKS1 CKS0 Initial value Read/Write Clock select 1/0 These bits select the baud rate generator's clock source Multiprocessor mode...
Bit 7 Description Asynchronous mode (Initial value) Synchronous mode For Smart Card Interface (SMIF Bit in SCMR Set to 1): Selects GSM mode for the smart card interface. Bit 7 Description The TEND flag is set 12.5 etu after the start bit (Initial value) The TEND flag is set 11.0 etu after the start bit Note: etu: Elementary time unit (time required to transmit one bit)
Bit 4 Description Even parity* (Initial value) Odd parity* Notes: 1. When even parity is selected, the parity bit added to transmit data makes an even number of 1s in the transmitted character and parity bit combined. Receive data must have an even number of 1s in the received character and parity bit combined.
For the relationship between the clock source, bit rate register setting, and baud rate, see section 12.2.8, Bit Rate Register (BRR). Bit 1 Bit 0 CKS1 CKS0 Description φ (Initial value) φ/4 φ/16 φ/64 12.2.6 Serial Control Register (SCR) SCR register enables or disables the SCI transmitter and receiver, enables or disables serial clock output in asynchronous mode, enables or disables interrupts, and selects the transmit/receive clock source.
The CPU can always read and write SCR. SCR is initialized to H'00 by a reset and in standby mode. Bit 7—Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt (TXI) requested when the TDRE flag in SSR is set to 1 due to transfer of serial transmit data from TDR to TSR.
Bit 4 Description Receiving disabled* (Initial value) Receiving enabled* Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags. These flags retain their previous values. 2. In the enabled state, serial receiving starts when a start bit is detected in asynchronous mode, or serial clock input is detected in synchronous mode.
For serial communication interface (SMIF bit in SCMR cleared to 0): These bits select the SCI clock source and enable or disable clock output from the SCK pin. Depending on the settings of CKE1 and CKE0, the SCK pin can be used for generic input/output, serial clock output, or serial clock input.
12.2.7 Serial Status Register (SSR) SSR is an 8-bit register containing multiprocessor bit values, and status flags that indicate the operating status of the SCI. TDRE RDRF ORER FER/ERS TEND MPBT Initial value R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Read/Write Multiprocessor bit transfer Value of multiprocessor bit to be transmitted Multiprocessor bit...
The CPU can always read and write SSR, but cannot write 1 in the TDRE, RDRF, ORER, PER, and FER flags. These flags can be cleared to 0 only if they have first been read while set to 1. The TEND and MPB flags are read-only bits that cannot be written. SSR is initialized to H'84 by a reset and in standby mode.
Bit 5—Overrun Error (ORER): Indicates that data reception ended abnormally due to an overrun error. Bit 5 ORER Description Receiving is in progress or has ended normally* (Initial value) [Clearing conditions] • The chip is reset or enters standby mode •...
For Smart Card Interface (SMIF Bit in SCMR Set to 1): Indicates the status of the error signal sent back from the receiving side during transmission. Framing errors are not detected in smart card interface mode. Bit 4 Description Normal reception, no error signal* (Initial value) [Clearing conditions] •...
Bit 2 TEND Description Transmission is in progress [Clearing condition] Read TDRE when TDRE = 1, then write 0 in TDRE End of transmission (Initial value) [Setting conditions] • The chip is reset or enters standby mode • The TE bit in SCR is cleared to 0 •...
Bit 0—Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit added to transmit data when a multiprocessor format in selected for transmitting in asynchronous mode. The MPBT bit setting is ignored in synchronous mode, when a multiprocessor format is not selected, or when the SCI cannot transmit.
Table 12.3 Examples of Bit Rates and BRR Settings in Asynchronous Mode φ (MHz) 2.097152 2.4576 Bit Rate (bit/s) Error (%) n Error (%) n Error (%) n Error (%) 141 0.03 148 -0.04 174 -0.26 212 0.03 103 0.16 108 0.21 127 0.00 155 0.16...
Table 12.4 Examples of Bit Rates and BRR Settings in Synchronous Mode φ (MHz) Rate (bit/s) n — — — — — — — — — — — — — — — — 124 2 249 3 124 — — 202 3 249 —...
The BRR setting is calculated as follows: Asynchronous mode: φ × 10 – 1 64 × 2 × B 2n–1 Synchronous mode: φ × 10 – 1 8 × 2 × B 2n–1 B: Bit rate (bit/s) N: BRR setting for baud rate generator (0 ≤ N ≤ 255) φ: System clock frequency (MHz) n: Baud rate generator input clock (n = 0, 1, 2, 3) (For the clock sources and values of n, see the following table.)
Table 12.5 shows the maximum bit rates in asynchronous mode for various system clock frequencies. Tables 12.6 and 12.7 show the maximum bit rates with external clock input. Table 12.5 Maximum Bit Rates for Various Frequencies (Asynchronous Mode) Settings φ (MHz) Maximum Bit Rate (bit/s) 62500 2.097152...
Table 12.6 Maximum Bit Rates with External Clock Input (Asynchronous Mode) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 0.7500 46875 3.6864 0.9216 57600 1.0000 62500 4.9152 1.2288 76800 1.2500 78125 1.5000 93750...
Table 12.7 Maximum Bit Rates with External Clock Input (Synchronous Mode) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) 0.3333 333333.3 0.6667 666666.7 1.0000 1000000.0 1.3333 1333333.3 1.6667 1666666.7 2.0000 2000000.0 2.3333 2333333.3 2.6667 2666666.7 3.0000 3000000.0 3.3333 3333333.3 4.1667 4166666.7...
Asynchronous Mode • Data length is selectable: 7 or 8 bits • Parity and multiprocessor bits are selectable, and so is the stop bit length (1 or 2 bits). These selections determine the communication format and character length. • In receiving, it is possible to detect framing errors, parity errors, overrun errors, and the break state.
Table 12.8 SMR Settings and Serial Communication Formats SMR Settings SCI Communication Format Multi- pro- Bit 7 Bit 6 Bit 2 Bit 5 Bit 3 Data cessor Parity Stop Bit STOP Mode Length Length Asyn- 8-bit data Absent Absent 1 bit chronous 2 bits mode...
12.3.2 Operation in Asynchronous Mode In asynchronous mode, each transmitted or received character begins with a start bit and ends with one or two stop bits. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCI are independent, so full-duplex communication is possible.
Table 12.10 Serial Communication Formats (Asynchronous Mode) SMR Settings Serial Communication Format and Frame Length STOP 8-bit data STOP 8-bit data STOP STOP 8-bit data STOP 8-bit data STOP STOP 7-bit data STOP 7-bit data STOP STOP 7-bit data STOP 7-bit data STOP STOP...
Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in SMR and bits CKE1 and CKE0 in SCR. For details of SCI clock source selection, see table 12.9.
Figure 12.4 shows a sample flowchart for initializing the SCI. Start of initialization Set the clock source in SCR. Clear the Clear TE and RE bits RIE, TIE, TEIE, MPIE, TE, and RE bits to to 0 in SCR 0. If clock output is selected in asynchronous mode, clock output starts Set CKE1 and CKE0 bits in SCR immediately after the setting is made in...
• Transmitting Serial Data (Asynchronous Mode): Figure 12.5 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. Initialize SCI initialization: the transmit data output function of the TxD pin is selected automatically. Start transmitting After the TE bit is set to 1, one frame of 1s is output, then transmission is possible.
In transmitting serial data, the SCI operates as follows: • The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. •...
• Receiving Serial Data (Asynchronous Mode): Figure 12.7 shows a sample flowchart for receiving serial data and indicates the procedure to follow. Initialize SCI initialization: the receive data input function of the RxD pin is selected automatically. Start receiving (2)(3) Receive error handling and break detection: if a receive error occurs, read the ORER, Read ORER, PER, and FER...
Error handling ORER= 1 Overrun error handling FER= 1 Break? Framing error handling Clear RE bit to 0 in SCR PER= 1 Parity error handling Clear ORER, PER, and FER flags to 0 in SSR <End> Figure 12.7 Sample Flowchart for Receiving Serial Data (cont)
In receiving, the SCI operates as follows: • The SCI monitors the communication line. When it detects a start bit (0 bit), the SCI synchronizes internally and starts receiving. • Receive data is stored in RSR in order from LSB to MSB. •...
Figure 12.8 shows an example of SCI receive operation in asynchronous mode. Start Parity Stop Start Parity Stop Data Data Idle (mark) state RDRF RXI interrupt RXI interrupt handler request Framing error, reads data in RDR and ERI interrupt clears RDRF flag to 0 1 frame request Figure 12.8 Example of SCI Receive Operation...
Communication Formats: Four formats are available. Parity bit settings are ignored when a multiprocessor format is selected. For details see table 12.10. Clock: See the description of asynchronous mode. Transmitting processor Serial communication line Receiving Receiving Receiving Receiving processor A processor B processor C processor D...
Initialize SCI initialization: the transmit data output function of the TxD pin is selected automatically. Start transmitting SCI status check and transmit data write: Read TDRE flag in SSR read SSR, check that the TDRE flag is 1, then write transmit data in TDR. Also set the MPBT flag to 0 or 1 in SSR.
In transmitting serial data, the SCI operates as follows: • The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. •...
SCI initialization: Initialize the receive data input function of the RxD pin is selected automatically. Start receiving ID receive cycle: set the MPIE bit to 1 in SCR. Set MPIE bit to 1 in SCR SCI status check and ID check: Read ORER and FER flags read SSR, check that the RDRF flag in SSR...
Error handling ORER= 1 Overrun error handling FER= 1 Break? Clear RE bit to 0 in SCR Framing error handling Clear ORER, PER, and FER flags to 0 in SSR <End> Figure 12.12 Sample Flowchart for Receiving Multiprocessor Serial Data (cont)
Figure 12.13 shows an example of SCI receive operation using a multiprocessor format. Start Stop Start Stop Data (ID1) Data (data1) Idle (mark) state MPIE RDRF RDR value RXI interrupt request RXI interrupt handler reads Not own ID, so MPIE No RXI interrupt MPB detection (multiprocessor interrupt)
12.3.4 Synchronous Operation In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver share the same clock but are otherwise independent, so full- duplex communication is possible.
Transmitting and Receiving Data: • SCI Initialization (Synchronous Mode): Before transmitting or receiving data, clear the TE and RE bits to 0 in SCR, then initialize the SCI as follows. When changing the communication mode or format, always clear the TE and RE bits to 0 before following the procedure given below.
• Transmitting Serial Data (Synchronous Mode): Figure 12.16 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. Initialize SCI initialization: the transmit data output function of the TxD pin is selected automatically. Start transmitting SCI status check and transmit data write: read SSR, check that the TDRE Read TDRE flag in SSR flag is 1, then write transmit data in...
In transmitting serial data, the SCI operates as follows. • The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. •...
Initialize SCI initialization: the receive data input function of the RxD pin is selected automatically. Start receiving Receive error handling: if a receive (2)(3) error occurs, read the ORER flag in Read ORER flag in SSR SSR, then after executing the necessary error handling, clear the ORER flag to 0.
Error handling Overrun error handling Clear ORER flag to 0 in SSR <End> Figure 12.18 Sample Flowchart for Serial Receiving (cont) In receiving, the SCI operates as follows: • The SCI synchronizes with serial clock input or output and synchronizes internally. •...
Figure 12.19 shows an example of SCI receive operation. Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER RXI interrupt RXI interrupt handler RXI interrupt Overrun error, request reads data in RDR and request ERI interrupt clears RDRF flag to 0...
• Transmitting and Receiving Data Simultaneously (Synchronous Mode): Figure 12.20 shows a sample flowchart for transmitting and receiving serial data simultaneously and indicates the procedure to follow. Initialize SCI initialization: the transmit data output function of the TxD pin and the read data input function of the TxD pin are selected, enabling simultaneous Start of transmitting and receiving transmitting and receiving.
12.4 SCI Interrupts The SCI has four interrupt request sources: transmit-end interrupt (TEI), receive-error (ERI), receive-data-full (RXI), and transmit-data-empty interrupt (TXI). Table 12.12 lists the interrupt sources and indicates their priority. These interrupts can be enabled or disabled by the TIE, RIE, and TEIE bits in SCR.
12.5 Usage Notes 12.5.1 Notes on Use of SCI Note the following points when using the SCI. TDR Write and TDRE Flag: The TDRE flag in SSR is a status flag indicating the loading of transmit data from TDR to TSR. The SCI sets the TDRE flag to 1 when it transfers data from TDR to TSR.
Break Detection and Processing: Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state the input from the RxD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. In the break state the SCI receiver continues to operate, so if the FER flag is cleared to 0 it will be set to 1 again.
The receive margin in asynchronous mode can therefore be expressed as shown in equation (1). D – 0.5 (1 + F) × 100% M = (0.5 – ) – (L – 0.5) F – ..(1) Receive margin (%) Ratio of clock frequency to bit rate (N = 16) Clock duty cycle (D = 0 to 1.0)
Switching from SCK Pin Function to Port Pin Function: • Problem in Operation: When switching the SCK pin function to the output port function (high- level output) by making the following settings while DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1 (synchronous mode), low-level output occurs for one half-cycle.
• Sample Procedure for Avoiding Low-Level Output: As this sample procedure temporarily places the SCK pin in the input state, the SCK/port pin should be pulled up beforehand with an external circuit. With DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1, make the following settings in the order shown.
Switchover between the normal serial communication interface and the smart card interface is controlled by a register setting. 13.1.1 Features Features of the smart card interface supported by the H8/3008 are listed below. • Asynchronous communication Data length: 8 bits Parity bit generation and checking ...
13.1.4 Register Configuration The smart card interface has the internal registers listed in table 13.2. The BRR, TDR, and RDR registers have their normal serial communication interface functions, as described in section 12, Serial Communication Interface. Table 13.2 Smart Card Interface Registers Channel Address* Name...
13.2 Register Descriptions This section describes the new or modified registers and bit functions in the smart card interface. 13.2.1 Smart Card Mode Register (SCMR) SCMR is an 8-bit readable/writable register that selects smart card interface functions. — — — —...
Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This function is used in combination with the SDIR bit to communicate with inverse-convention cards.* The SINV bit does not affect the logic level of the parity bit. For parity settings, see section 13.3.4, Register Settings.
13.2.2 Serial Status Register (SSR) The function of SSR bit 4 is modified in smart card interface mode. This change also causes a modification to the setting conditions for bit 2 (TEND). TDRE RDRF ORER TEND MPBT Initial value Read/Write R/(W)* R/(W)* R/(W)*...
Bits 3 to 0: These bits operate as in normal serial communication. For details see section 12.2.7, Serial Status Register (SSR). The setting conditions for transmit end (TEND), however, are modified as follows. Bit 2 TEND Description Transmission is in progress [Clearing condition] Software reads TDRE while it is set to 1, then writes 0 in the TDRE flag.
Bit 7 Description Normal smart card interface mode operation • The TEND flag is set 12.5 etu after the beginning of the start bit. • Clock output on/off control only. (Initial value) GSM mode smart card interface mode operation • The TEND flag is set 11.0 etu after the beginning of the start bit.
CLK pin of the smart card. If the smart card uses an internal clock, this connection is unnecessary. The reset signal should be output from one of the H8/3008’s generic ports. In addition to these pin connections. power and ground connections will normally also be...
Data line Clock line H8/3008 Px (port) chip Reset line Smart card Card-processing device Figure 13.2 Smart Card Interface Connection Diagram Note: Setting both TE and RE to 1 without connecting a smart card enables closed transmission/reception, allowing self-diagnosis to be carried out.
No parity error Output from transmitting device Parity error Output from transmitting device Output from receiving Legend device Start bit D0 to D7: Data bits Parity bit Error signal Figure 13.3 Smart Card Interface Data Format The operating sequence is as follows. 1.
13.3.4 Register Settings Table 13.3 shows a bit map of the registers used in the smart card interface. Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described in this section. Table 13.3 Smart Card Interface Register Settings Register Address Bit 7...
In the H8/3008, inversion specified by the SINV bit applies only to the data bits, D7 to D0. For parity bit inversion, the O/E bit in SMR must be set to odd parity mode. This applies to both...
13.3.5 Clock Only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock for the smart card interface. The bit rate is set with the bit rate register (BRR) and the CKS1 and CKS0 bits in the serial mode register (SMR). The equation for calculating the bit rate is shown below.
The following equation calculates the bit rate register (BRR) setting from the operating frequency and bit rate. N is an integer from 0 to 255, specifying the value with the smaller error. φ × 10 – 1 1488 × 2 ×...
13.3.6 Transmitting and Receiving Data Initialization: Before transmitting or receiving data, the smart card interface must be initialized as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. 1. Clear the TE and RE bits to 0 in the serial control register (SCR). 2.
For details, see Interrupt Operations in this section. Serial data Guard time (1) GM = 0 TEND 12.5 etu (2) GM = 1 TEND 11.0 etu Figure 13.4 Timing of TEND Flag Setting...
Start Initialization Start transmitting FER/ERS = 0? Error handling TEND = 1? Write transmit data in TDR, and clear TDRE flag to 0 in SSR All data transmitted? FER/ERS = 0? Error handling TEND = 1? Clear TE bit to 0 Figure 13.5 Sample Transmission Processing Flowchart...
(shift register) 1. Data write Data 1 2. Transfer from TDR to TSR Data 1 Data 1 Data remains in TDR Data 1 I/O signal 3. Serial data output Data 1 output In case of normal transmission: TEND flag is set In case of transmit error: ERS flag is set Steps 2 and 3 above are repeated until the...
Start Initialization Start receiving ORER = 0 and PER = 0? Error handling RDRF = 1? Read RDR and clear RDRF flag to 0 in SSR All data received? Clear RE bit to 0 Figure 13.8 Sample Reception Processing Flowchart The above procedure may include interrupt handling.
When switching from transmit mode to receive mode, first confirm that the transmit operation has been completed, then start from initialization, clearing TE to 0 and setting RE to 1. The TEND flag can be used to check that the transmit operation has been completed. Fixing Clock Output: When the GM bit is set to 1 in SMR, clock output can be fixed by means of the CKE1 and CKE0 bits in SCR.
Examples of Operation in GSM Mode: When switching between smart card interface mode and software standby mode, use the following procedures to maintain the clock duty cycle. • Switching from smart card interface mode to software standby mode 1. Set the P9 data register (DR) and data direction register (DDR) to the values for the fixed output state in software standby mode.
13.4 Usage Notes The following points should be noted when using the SCI as a smart card interface. Receive Data Sampling Timing and Receive Margin in Smart Card Interface Mode: In smart card interface mode, the SCI operates on a base clock with a frequency of 372 times the transfer rate.
The receive margin can therefore be expressed as follows. Receive margin in smart card interface mode: D – 0.5 (1 + F) × 100% M = (0.5 – ) – (L – 0.5) F – M: Receive margin (%) N: Ratio of clock frequency to bit rate (N = 372) D: Clock duty cycle (L = 0 to 1.0) L: Frame length (L =10) F: Absolute deviation of clock frequency...
TEND Figure 13.13 Retransmission in SCI Transmit Mode Note on Block Transfer Mode Support: The smart card interface installed in the H8/3008 supports an IC