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Notes on Use of Boot Mode:
1. When the chip comes out of reset in boot mode, it measures the low period of the input at the
SCI's SI1 pin. The reset should end with SI1 pin high. After the reset ends, it takes about 100
states for the chip to get ready to measure the low period of the SI1 pin input.
2. In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all
flash memory blocks are erased. Boot mode is for use when user program mode is
unavailable, such as the first time on-board programming is performed, or if the program
activated in user program mode is accidentally erased.
3. Interrupts cannot be used while the flash memory is being programmed or erased.
4. The SI1 and SO1 pins should be pulled up on the board.
5. Before branching to the programming control program (RAM area TBD), the chip terminates
transmit and receive operations by the on-chip SCI (channel 1) (by clearing the RE and TE bits
in SCR to 0), but the adjusted bit rate value remains set in BRR. The transmit data output pin,
SO1, goes to the high-level output state (P21PCR = 1, P21PDR = 1).
The contents of the CPU's internal general registers are undefined at this time, so these
registers must be initialized immediately after branching to the programming control program.
In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack
area must be specified for use by the programming control program.
The initial values of other on-chip registers are not changed.
6. Boot mode can be entered by making the pin settings shown in table 7.4 and executing a reset-
start.
When the chip detects the boot mode setting at reset release
Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting
the FWE pin and mode pins, and executing reset release
WDT overflow reset.
If the mode pin input levels are changed in boot mode, the boot mode state will be maintained
in the microcomputer, and boot mode continued, unless a reset occurs. However, the FWE pin
must not be driven low while the boot program is running or flash memory is being
programmed or erased.
Notes: 1. Mode pin and FWE pin input must satisfy the mode programming setup time (t
states) with respect to the reset release timing.
*1
, it retains that state internally.
*1
. Boot mode can also be cleared by a
Rev. 1.0, 02/00, page 145 of 1141
= 4
MDS
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