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28.2
Register Description
28.2.1
Slice Even- (Odd-) Field Mode Register (SEVFD, SODFD)
(1) Slice even-field mode register
15
Bit:
EVNIE
Initial value:
R/W:
R/W
Bit:
SLVLE2
Initial value:
R/W:
R/W
(2) Slice odd-field mode register
15
Bit:
ODDIE
Initial value:
R/W:
R/W
Bit:
SLVLO2
Initial value:
R/W:
R/W
Note: * Only 0 can be written to clear the flag.
The SEVFD and SODFD control the start bit detection starting position, slice voltage level, data
sampling delay time, and interrupts. The SEVFD holds settings for even fields, and the SODFD
holds settings for odd fields. When reset, when the module is stopped, in sleep mode, in standby
mode, in watch mode, in subactive mode, or in subsleep mode, the SEVFD and SODFD are both
initialized to H'2000.
The SEVFD and SODFD are 16-bit read/write registers; however, rewriting of SEVFD or SODFD
should be performed after output of an even- (odd-) field slice completion interrupt. During data
slice operations, if SEVFD or SODFD is rewritten, a malfunction will result; do not perform
rewriting during data slice operation.
14
13
EVNIF
—
0
0
R/(W)*
—
7
6
SLVLE1
SLVLE0
0
0
R/W
R/W
14
13
ODDIF
—
0
0
R/(W)*
—
7
6
SLVLO1
SLVLO0
0
0
R/W
R/W
12
11
STBE4
STBE3
1
0
R/W
R/W
5
4
DLYE4
DLYE3
0
0
R/W
R/W
12
11
STBO4
STBO3
1
0
R/W
R/W
5
4
DLYO4
DLYO3
0
0
R/W
R/W
10
STBE2
STBE1
0
0
R/W
R/W
3
2
DLYE2
DLYE1
0
0
R/W
R/W
10
STBO2
STBO1
0
0
R/W
R/W
3
2
DLYO2
DLYO1
0
0
R/W
R/W
Rev. 1.0, 02/00, page 803 of 1141
9
8
STBE0
0
0
R/W
1
0
DLYE0
0
0
R/W
9
8
STBO0
0
0
R/W
1
0
DLYO0
0
0
R/W
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