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(1) If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
(2) When interrupt requests are sent to the interrupt controller, a control level 1 interrupt,
according to the control level set in ICR, has priority for selection, and other interrupt requests
are held pending. If a number of interrupt requests with the same control level setting are
generated at the same time, the interrupt request with the highest priority according to the
priority system shown in table 6.4 is selected.
(3) The I bit is then referenced. If the I bit is cleared to 0, the UI bit has no effect.
An interrupt request set to interrupt control level 0 is accepted when the I bit is cleared to 0. If
the I bit is set to 1, only NMI* and address trap interrupts are accepted, and other interrupt
requests are held pending.
An interrupt request set to interrupt control level 1 has priority over an interrupt request set to
interrupt control level 0, and is accepted if the I bit is cleared to 0, or if the I bit is set to 1 and
the UI bit is cleared to 0.
When both the I bit and the UI bit are set to 1, only NMI* and address trap interrupts are
accepted, and other interrupt requests are held pending.
(4) When an interrupt request is accepted, interrupt exception handling starts after execution of the
current instruction has been completed.
(5) The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
(6) Next, the I and UI bits in CCR are set to 1. This masks all interrupts except NMI* and address
trap.
(7) A vector address is generated for the accepted interrupt, and execution of the interrupt
handling routine starts at the address indicated by the contents of that vector address.
Note: * In this LSI, the NMI interrupt is generated by the watchdog timer.
Rev. 1.0, 02/00, page 116 of 1141
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