Hitachi H8/3062 Hardware Manual

Single-chip microcomputer
Hide thumbs

Advertisement

Quick Links

Table of Contents
HD64F3062, HD64F3062R, HD64F3062A
ADE-602-136B
Rev. 3.0
3/20/00
Hitachi, Ltd.
Hitachi Single-Chip Microcomputer
H8/3062 Series
H8/3062F-ZTAT™
H8/3064F-ZTAT™
Hardware Manual
H8/3062
HD6433062
H8/3061
HD6433061
H8/3060
HD6433060
HD64F3064

Advertisement

Table of Contents
loading

  Also See for Hitachi H8/3062

  Related Manuals for Hitachi H8/3062

  Summary of Contents for Hitachi H8/3062

  • Page 1 Hitachi Single-Chip Microcomputer H8/3062 Series H8/3062 HD6433062 H8/3061 HD6433061 H8/3060 HD6433060 H8/3062F-ZTAT™ HD64F3062, HD64F3062R, HD64F3062A H8/3064F-ZTAT™ HD64F3064 Hardware Manual ADE-602-136B Rev. 3.0 3/20/00 Hitachi, Ltd.
  • Page 2 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.
  • Page 3 This version offers flexibility in the development of new products to meet fast-changing market needs. This manual describes the H8/3062 Series hardware. For details of the instruction set, refer to the H8/300H Series Programming Manual.
  • Page 4 Product code descriptions amended Table 1.1 Features CPU Description amended Figure 1.1 Block Diagram Notes amended Table 1.2 Comparison of H8/3062 Series Pin Added Arrangements Figure 1.4 Pin Arrangement of H8/3064F-ZTAT and Added H8/3062F-ZTAT A-Mask Version(FP-100B or TFP- 100B Package, Top View) Figure 1.5...
  • Page 5 Table 3.1 Operating Mode Selection Table amended 3.1.1 Operating Mode Selection Description added 3.4.5 Mode 5 Description added 3.6.1 Comparison of H8/3062 Series Memory Maps Added Figure 3.4 H8/3064F-ZTAT Memory Map in Each Added Operating Mode 80, 81 Figure 3.4 H8/3064F-ZTAT Memory Map in Each...
  • Page 6 20 MHz and 25 MHz added Frequencies (Smart Card Interface Mode) Figure 13.10 Procedure for Stopping and Restarting Amended the Clock 13.4 Usage Notes Description added 14.1 Overview Description added 14.1.1 Features High-speed conversion 25 MHz added Table 16.1 H8/3062 Series On-Chip RAM Added Specifications...
  • Page 7 17.9 Flash Memory Programming and Erasing 9 added Precautions 17.9 Flash Memory Programming and Erasing Note added Precautions Figure 17.19 ROM Block Diagram (H8/3062 Mask Amended ROM Version) 17.11 Notes on Ordering Mask ROM Version Chips 4 added 17.12 Notes when Converting the F-ZTAT Application...
  • Page 8 22.4 Electrical Characteristics of H8/3062F-ZTAT A- Added Mask Version Figure 22.19 Basic Bus Cycle: Three-State Access Amended with One Wait State Table B.1 Comparison of H8/3062 Series Internal I/O Table added Register Specifications 779 to B.2 Address List (H8/3064F-ZTAT) Table added 789 to B.3 Address List (H8/3062F-ZTAT A-Mask Version)
  • Page 9 There are seven members of the H8/3062 Series: the H8/3062F-ZTAT, H8/3062F-ZTAT R-mask version, H8/3062F-ZTAT A-mask version, and H8/3064F-ZTAT (all with on-chip flash memory), and the H8/3062 mask ROM version, H8/3061 mask ROM version, and H8/3060 mask ROM version. The specifications of these products are compared below.
  • Page 10 H8/3062 Mask ROM Version, H8/3061 Mask ROM Version, H8/3062F-ZTAT H8/3060 Mask H8/3062F-ZTAT H8/3062F-ZTAT R-Mask Version ROM Version H8/3064F-ZTAT A-Mask Version Address Compatible with Address update Address update Address update Address update output previous H8/300H mode 1 or 2 mode 1 or 2...
  • Page 11: Table Of Contents

    Contents Section 1 Overview ......................Overview ..........................Block Diagram........................Pin Description ........................1.3.1 Pin Arrangement ....................1.3.2 Pin Functions......................12 1.3.3 Pin Assignments in Each Mode ................16 Notes on H8/3062F-ZTAT R-Mask Version ..............20 1.4.1 Pin Arrangement ....................20 1.4.2 Product Type Names and Markings..............
  • Page 12 Mode 6 ........................70 3.4.7 Mode 7 ........................70 Pin Functions in Each Operating Mode................71 Memory Map in Each Operating Mode................72 3.6.1 Comparison of H8/3062 Series Memory Maps ............ 72 3.6.2 Reserved Areas...................... 73 Section 4 Exception Handling ..................83 Overview ..........................
  • Page 13 4.2.2 Reset Sequence...................... 86 4.2.3 Interrupts after Reset ..................... 89 Interrupts ..........................90 Trap Instruction ........................90 Stack Status after Exception Handling ................91 Notes on Stack Usage......................92 Section 5 Interrupt Controller ..................95 Overview ..........................95 5.1.1 Features ......................... 95 5.1.2 Block Diagram ......................
  • Page 14 6.2.5 Bus Control Register (BCR) ................. 131 6.2.6 Chip Select Control Register (CSCR)..............133 6.2.7 Address Control Register (ADRCR)..............134 Operation ..........................135 6.3.1 Area Division ......................135 6.3.2 Bus Specifications ....................138 6.3.3 Memory Interfaces ....................139 6.3.4 Chip Select Signals....................139 6.3.5 Address Output Method ..................
  • Page 15 7.7.1 Overview ....................... 180 7.7.2 Register Descriptions .................... 181 Port 7 ..........................184 7.8.1 Overview ....................... 184 7.8.2 Register Description....................185 Port 8 ..........................186 7.9.1 Overview ....................... 186 7.9.2 Register Descriptions .................... 187 7.10 Port 9 ..........................191 7.10.1 Overview ....................... 191 7.10.2 Register Descriptions ....................
  • Page 16 8.4.4 PWM Mode ......................257 8.4.5 Phase Counting Mode ................... 261 8.4.6 16-Bit Timer Output Timing ................. 263 Interrupts ..........................264 8.5.1 Setting of Status Flags................... 264 8.5.2 Timing of Clearing of Status Flags ............... 266 8.5.3 Interrupt Sources ....................267 Usage Notes........................
  • Page 17 9.7.8 Contention between Compare Matches A and B ..........316 9.7.9 8TCNT Operation and Internal Clock Source Switchover ........316 Section 10 Programmable Timing Pattern Controller (TPC) ........319 10.1 Overview ..........................319 10.1.1 Features ......................... 319 10.1.2 Block Diagram ...................... 320 10.1.3 Pin Configuration ....................
  • Page 18 11.3.2 Interval Timer Operation ..................354 11.3.3 Timing of Setting of Overflow Flag (OVF)............354 11.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) ........355 11.4 Interrupts ..........................356 11.5 Usage Notes........................356 Section 12 Serial Communication Interface ..............
  • Page 19 13.3.2 Pin Connections ....................425 13.3.3 Data Format......................426 13.3.4 Register Settings....................428 13.3.5 Clock ........................430 13.3.6 Transmitting and Receiving Data................432 13.4 Usage Notes........................439 Section 14 A/D Converter ....................443 14.1 Overview ..........................443 14.1.1 Features ......................... 443 14.1.2 Block Diagram ......................
  • Page 20 17.8.2 Notes on Use of PROM Mode ................510 17.9 Flash Memory Programming and Erasing Precautions............511 17.10 Mask ROM (H8/3062 Mask ROM Version, H8/3061 Mask ROM Version, H8/3060 Mask ROM Version) Overview ................516 17.10.1 Block Diagram ...................... 516 17.11 Notes on Ordering Mask ROM Version Chips ..............
  • Page 21 18.2 Features ..........................521 18.2.1 Block Diagram ...................... 522 18.2.2 Pin Configuration ....................523 18.2.3 Register Configuration ..................523 18.3 Register Descriptions......................524 18.3.1 Flash Memory Control Register 1 (FLMCR1)............524 18.3.2 Flash Memory Control Register 2 (FLMCR2)............527 18.3.3 Erase Block Register 1 (EBR1) ................528 18.3.4 Erase Block Register 2 (EBR2) ................
  • Page 22 19.3.2 Flash Memory Control Register 2 (FLMCR2)............577 19.3.3 Erase Block Register (EBR).................. 578 19.3.4 RAM Control Register (RAMCR) ................ 579 19.4 Overview of Operation ....................... 581 19.4.1 Mode Transitions ....................581 19.4.2 On-Board Programming Modes................583 19.4.3 Flash Memory Emulation in RAM................ 585 19.4.4 Block Configuration....................
  • Page 23 21.7 System Clock Output Disabling Function................641 Section 22 Electrical Characteristics ................643 22.1 Electrical Characteristics of H8/3062 Mask ROM Version, H8/3061 Mask ROM Version, and H8/3060 Mask ROM Version........645 22.1.1 Absolute Maximum Ratings.................. 645 22.1.2 DC Characteristics ....................646 22.1.3 AC Characteristics ....................
  • Page 24 Number of States Required for Execution................759 Appendix B Internal I/O Registers ................. 768 Address List (H8/3062F-ZTAT, H8/3062F-ZTAT R-Mask Version, H8/3062 Mask ROM Version, H8/3061 Mask ROM Version, H8/3060 Mask ROM Version) ................... 769 Address List (H8/3064F-ZTAT) ..................779 Address List (H8/3062F-ZTAT A-Mask Version) ............789 Functions ..........................
  • Page 25 Appendix G Package Dimensions ................... 914 Appendix H Comparison of H8/300H Series Product Specifications ....917 Differences between H8/3067 and H8/3062 Series, H8/3048 Series, H8/3007 and H8/3006, and H8/3002.................. 917 Comparison of Pin Functions of 100-Pin Package Products (FP-100B, TFP-100B)..920...
  • Page 26: Section 1 Overview

    (modes 1 to 7) include two single-chip modes and five expanded modes. In addition to its mask ROM versions, the H8/3062 Series has F-ZTAT™* versions with on-chip flash memory that allows programs to be freely rewritten by the user. This version enables users to respond quickly and flexibly to changing application specifications, growing production volumes, and other conditions.
  • Page 27 Multiply clock rate /subtract /divide H8/3062F-ZTZT 20 MHz 100 ns 700 ns H8/3062F-ZTAT R-Mask version H8/3062 (mask ROM version) H8/3061 (mask ROM version) H8/3060 (mask ROM version) H8/3064F-ZTAT 25 MHz 80 ns 560 ns H8/3062F-ZTAT A-Mask version 16-Mbyte address space Instruction features •...
  • Page 28 Feature Description • Bus controller Address space can be partitioned into eight areas, with independent bus specifications in each area • Chip select output available for areas 0 to 7 • 8-bit access or 16-bit access selectable for each area •...
  • Page 29 Feature Description • A/D converter Resolution: 10 bits • Eight channels, with selection of single or scan mode • Variable analog conversion voltage range • Sample-and-hold function • A/D conversion can be started by an external trigger or 8-bit timer compare- match •...
  • Page 30 Feature Description Product lineup Package Product Type Model (Hitachi Package Code) H8/3062F-ZTAT 5 V operation HD64F3062F 100-pin QFP (FP-100B) HD64F3062TE 100-pin TQFP (TFP-100B) HD64F3062FP 100-pin QFP (FP-100A) H8/3062F-ZTAT 5 V operation HD64F3062RF 100-pin QFP (FP-100B) R-mask version HD64F3062RTE 100-pin TQFP (TFP-100B)
  • Page 31: Block Diagram

    Block Diagram Figure 1.1 shows an internal block diagram. Port 3 Port 4 Address bus P5 /A Data bus (upper) P5 /A P5 /A Data bus (lower) P5 /A EXTAL P2 /A XTAL P2 /A STBY H8/300H CPU P2 /A P2 /A RESO/FWE P2 /A...
  • Page 32: Pin Description

    1.3.1 Pin Arrangement The pin arrangement of the H8/3062 Series is shown in figures 1.2 to 1.5. Differences in the H8/3062 Series pin arrangements are shown in table 1.2. The 5 V operation models of the H8/3064F-ZTAT and the H8/3062F-ZTAT A-mask version have a V pin.
  • Page 33 Note: * Functions as RESO in the mask ROM versions, and as FWE in the on-chip flash memory versions. Figure 1.2 Pin Arrangement of H8/3062F-ZTAT, H8/3062F-ZTAT R-Mask Version, H8/3062 Mask ROM Version, H8/3061 Mask ROM Version, and H8/3060 Mask ROM Version...
  • Page 34 Note: * Functions as RESO in the mask ROM versions, and as FWE in the on-chip flash memory versions. Figure 1.3 Pin Arrangement of H8/3062F-ZTAT, H8/3062F-ZTAT R-Mask Version, H8/3062 Mask ROM Version, H8/3061 Mask ROM Version, and H8/3060 Mask ROM Version...
  • Page 35 P7 /AN P7 /AN P7 /AN P7 /AN P7 /AN P7 /AN P7 /AN /DA P7 /AN /DA Top view /IRQ (FP-100B, TFP-100B) /IRQ ADTRG/CS /IRQ TCLKA/TP TCLKB/TP TCLKC/TIOCA TCLKD/TIOCB /TIOCA /TIOCB /TIOCA /TIOCB 0.1 µF Note: * V pin in 5 V operation models, V pin in 3 V operation models.
  • Page 36 Top view (FP-100A) /IRQ /IRQ /IRQ /IRQ /ADTRG /TCLKA D /P3 /TCLKB D /P3 /TIOCA /TCLKC D /P3 /TIOCB /TCLKD D /P3 /TIOCA D /P3 /TIOCB D /P3 0.1 µF Note: * V pin in 5 V operation models, V pin in 3 V operation models.
  • Page 37: Pin Functions

    1.3.2 Pin Functions Table 1.3 summarizes the pin functions. The H8/3064F-ZTAT and the H8/3062F-ZTAT A-mask version 5 V operation models have a V pin, and require the connection of an external capacitor. Table 1.3 Pin Functions Pin No. FP-100B Type Symbol TFP-100B FP-100A I/O Name and Function...
  • Page 38 Pin No. FP-100B Type Symbol TFP-100B FP-100A I/O Name and Function System Input Reset input: When driven low, this pin resets control the chip. This pin must be driven low at power- RESO Output Reset output (On-chip mask ROM versions): Outputs the reset signal generated by the watchdog timer to external devices Input Write enable signal (On-chip flash memory...
  • Page 39 Pin No. FP-100B Type Symbol TFP-100B FP-100A I/O Name and Function 16-bit TCLKD to 96 to 93 98 to95 Input Clock input D to A: External clock inputs timer TCLKA TIOCA 99, 97, 95 1, 99, 97 Input/ Input capture/output compare A2 to A0: TIOCA output GRA2 to GRA0 output compare or input...
  • Page 40 B data direction register (PBDDR). Notes: 1. In the H8/3062F-ZTAT, H8/3062F-ZTAT R-mask version, H8/3062 mask ROM version, H8/3061 mask ROM version, and H8/3060 mask ROM version 2. In the H8/3064F-ZTAT and the H8/3062F-ZTAT A-mask version (5 V operation models).
  • Page 41: Pin Assignments In Each Mode

    1.3.3 Pin Assignments in Each Mode Table 1.4 lists the pin assignments in each mode. Table 1.4 Pin Assignments in Each Mode (FP-100B or TFP-100B, FP-100A) Pin No. Pin Name FP-100B TFP-100B FP-100A Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7...
  • Page 42 Pin No. Pin Name FP-100B TFP-100B FP-100A Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 /WAIT /WAIT /WAIT /WAIT /WAIT...
  • Page 43 Pin No. Pin Name FP-100B TFP-100B FP-100A Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 /BREQ P6 /BREQ P6 /BREQ P6 /BREQ P6 /BREQ P6 /BACK P6 /BACK P6 /BACK P6 /BACK P6 /BACK P6 φ...
  • Page 44 Functions as the programming control signal in modes 5 and 7. 4. Functions as V in the H8/3062F-ZTAT, H8/3062F-ZTAT R-mask version, H8/3062 mask ROM version, H8/3061 mask ROM version, and H8/3060 mask ROM version. In the H8/3064F-ZTAT and the H8/3062F-ZTAT A-mask version, this pin functions as V in 5 V operation models, and as V in 3 V operation models.
  • Page 45: Notes On H8/3062F-Ztat R-Mask Version

    Notes on H8/3062F-ZTAT R-Mask Version There are two models with on-chip flash memory in the H8/3062 Series: the H8/3062F-ZTAT (HD64F3062) and the H8/3062F-ZTAT R-mask version (HD64F3062R). Points to be noted when using the H8/3062F-ZTAT R-mask version are given below. 1.4.1...
  • Page 46: Product Type Names And Markings

    Table 1.5 Differences in H8/3062F-ZTAT and H8/3062F-ZTAT R-Mask Version Markings H8/3062F-ZTAT H8/3062F-ZTAT R-Mask Version TFP-100 Product type name HD64F3062TE HD64F3062RTE Sample markings H8/3062 H8/3062 64F3062TE20 64F3062TE20 JAPAN JAPAN “R” is printed above the type name FP-100B Product type name HD64F3062F...
  • Page 47: Notes On H8/3064F-Ztat And H8/3062F-Ztat A-Mask Version

    H8/3062F-ZTAT A-mask version are the same as for the H8/3062F-ZTAT R-mask version. Notes on H8/3064F-ZTAT and H8/3062F-ZTAT A-Mask Version The H8/3062 Series includes one model with 128-kbyte on-chip flash memory, the H8/3062F- ZTAT A-mask version (HD64F3062A) developed on the basis of the H8/3062F-ZTAT R-mask version, and one model with 256-kbyte large-capacity on-chip flash memory, the H8/3064F-ZTAT (HD64F3064).
  • Page 48: Product Type Names And Markings

    Differences in H8/3062F-ZTAT R-Mask Version, H8/3062F-ZTAT A-Mask Version, and H8/3064F-ZTAT Markings H8/3062F-ZTAT H8/3062F-ZTAT R-Mask Version A-Mask Version H8/3064F-ZTAT TFP-100 Product type HD64F3062RTE HD64F3062ATE HD64F3064TE name Sample H8/3062 H8/3062 H8/3064 markings 64F3062TE20 64F3062TE20 64F3064TE20 JAPAN JAPAN JAPAN “A” is printed above the type name FP-100B Product type...
  • Page 49 (Connect the V power supply to other V pins as usual.) Note that the V output pin occupies the same location as a V pin in the H8/3062F-ZTAT R-mask version and on-chip mask ROM models (H8/3062, H8/3061, and H8/3060). power supply External capacitor 0.1 µF...
  • Page 50: Note On Changeover To Mask Rom Version

    Note on Changeover to Mask ROM Version Care is required when changing from the H8/3062F-ZTAT A-mask version with on-chip flash memory to a model with on-chip mask ROM (H8/3062, H8/3061, or H8/3060). An external capacitor must be connected to the V pin of the H8/3062F-ZTAT A-mask version (5 V model).
  • Page 51: Setting Oscillation Settling Wait Time

    Setting Oscillation Settling Wait Time When software standby mode is used, after exiting software standby mode a wait period must be provided to allow the clock to stabilize. Select the length of time for which the CPU and peripheral functions are to wait by setting bits STS2 to STS0 in the system control register (SYSCR) and bits DIV1 and DIV0 in the division ratio control register (DIVCR) according to the operating frequency of the chip.
  • Page 52: Cpu

     All frequently-used instructions execute in two to four states  Maximum clock frequency: 20 MHz (H8/3062F-ZTAT, H8/3062F-ZTAT R- Mask version, H8/3062, H8/3061, H8/3060) 25 MHz (H8/3064F-ZTAT, H8/3062F-ZTAT A- Mask version)  8/16/32-bit register-register add/subtract: 100 ns@20 MHz (80 ns@25 MHz) ...
  • Page 53: Differences From H8/300 Cpu

     16 ÷ 8-bit register-register divide: 700 ns@20 MHz (560 ns@25 MHz)  16 × 16-bit register-register multiply: 1.1 µs@20 MHz (0.88 µs@25 MHz)  32 ÷ 16-bit register-register divide: 1.1 µs@20 MHz (0.88 µs@25 MHz) • Two CPU operating modes ...
  • Page 54: Address Space

    Address Space Figure 2.2 shows a simple memory map for the H8/3062 Series. The H8/300H CPU can address a linear address space with a maximum size of 64 kbytes in normal mode, and 16 Mbytes in advanced mode. For further details see section 3.6, Memory Map in Each Operating Mode.
  • Page 55: Register Configuration

    Register Configuration 2.4.1 Overview The H8/300H CPU has the internal registers shown in figure 2.3. There are two types of registers: general registers and control registers. General Registers (ERn) (SP) Control Registers (CR) 6 5 4 3 2 1 0 I UI H U N Z V C Legend: Stack pointer...
  • Page 56: 2.4.2 General Registers

    2.4.2 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used without distinction between data registers and address registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or as address registers, they are designated by the letters ER (ER0 to ER7).
  • Page 57: Control Registers

    Free area SP (ER7) Stack area Figure 2.5 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC) and the 8-bit condition code register (CCR). Program Counter (PC): This 24-bit counter indicates the address of the next instruction the CPU will execute.
  • Page 58: Initial Cpu Register Values

    Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0—Carry Flag (C): Set to 1 when a carry is generated by execution of an operation, and cleared to 0 otherwise. Used by: •...
  • Page 59: Data Formats

    Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.
  • Page 60: Memory Data Formats

    General Data Type Register Data Format Word data Word data Longword data Legend: ERn: General register General register E General register R MSB: Most significant bit LSB: Least significant bit Figure 2.7 General Register Data Formats 2.5.2 Memory Data Formats Figure 2.8 shows the data formats on memory.
  • Page 61 Data Type Address Data Format 1-bit data Address L Byte data Address L Word data Address 2M Address 2M + 1 Address 2N Longword data Address 2N + 1 Address 2N + 2 Address 2N + 3 Figure 2.8 Memory Data Formats When ER7 (SP) is used as an address register to access the stack, the operand size should be word size or longword size.
  • Page 62: Instruction Set

    Notes: 1. POP.W Rn is identical to MOV.W @SP+, Rn. PUSH.W Rn is identical to MOV.W Rn, @–SP. POP.L ERn is identical to MOV.L @SP+, Rn. PUSH.L ERn is identical to MOV.L Rn, @–SP. 2. Not available in the H8/3062 Series. 3. Bcc is a generic branching instruction.
  • Page 63: Instructions And Addressing Modes

    2.6.2 Instructions and Addressing Modes Table 2.2 indicates the instructions available in the H8/300H CPU. Table 2.2 Instructions and Addressing Modes Addressing Modes (d:16, (d:24, @ERn+/ (d:8, (d:16, Function Instruction @ERn ERn) ERn) @–ERn aa:8 aa:16 aa:24 aa:8 — Data —...
  • Page 64: Tables Of Instructions Classified By Function

    2.6.3 Tables of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The operation notation used in these tables is defined next. Operation Notation General register (destination)* General register (source)* General register* General register (32-bit register or address register)* (EAd) Destination operand (EAs)
  • Page 65 Table 2.3 Data Transfer Instructions Instruction Size* Function (EAs) → Rd, Rs → (EAd) B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. (EAs) → Rd MOVFPE Cannot be used in this LSI.
  • Page 66 Table 2.4 Arithmetic Operation Instructions Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd ADD,SUB B/W/L Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from data in a general register.
  • Page 67 Instruction Size* Function Rd ÷ Rs → Rd DIVXU Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder Rd ÷...
  • Page 68 Table 2.5 Logic Operation Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd B/W/L Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd B/W/L Performs a logical OR operation on a general register and another general register or immediate data.
  • Page 69 Table 2.7 Bit Manipulation Instructions Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower 3 bits of a general register.
  • Page 70 Instruction Size* Function C ∨ (<bit-No.> of <EAd>) → C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. C ∨...
  • Page 71 Table 2.8 Branching Instructions Instruction Size Function — Branches to a specified address if address specified condition is met. The branching conditions are listed below. Mnemonic Description Condition BRA (BT) Always (true) Always BRN (BF) Never (false) Never C ∨ Z = 0 High C ∨...
  • Page 72 Table 2.9 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling — Returns from an exception-handling routine SLEEP — Causes a transition to the power-down state (EAs) → CCR Moves the source operand contents to the condition code register. The condition code register size is one byte, but in transfer from memory, data is read by word access.
  • Page 73: 2.6.4 Basic Instruction Formats

    Table 2.10 Block Transfer Instruction Instruction Size Function if R4L ≠ 0 then EEPMOV.B — @ER5+ → @ER6+, R4L – 1 → R4L repeat until R4L = 0 else next; if R4 ≠ 0 then EEPMOV.W — @ER5+ → @ER6+, R4 – 1 → R4 repeat until R4 = 0...
  • Page 74: Notes On Use Of Bit Manipulation Instructions

    Operation field only NOP, RTS, etc. Operation field and register fields ADD.B Rn, Rm, etc. Operation field, register fields, and effective address extension MOV.B @(d:16, Rn), Rm EA (disp) Operation field, effective address extension, and condition field EA (disp) BRA d:8 Figure 2.9 Instruction Formats 2.6.5 Notes on Use of Bit Manipulation Instructions...
  • Page 75 Before Execution of BCLR Instruction Input/output Input Input Output Output Output Output Output Output Execution of BCLR Instruction BCLR #0, P4DDR Execute BCLR instruction on DDR After Execution of BCLR Instruction Input/output Output Output Output Output Output Output Output Input Explanation: To execute the BCLR instruction, the CPU begins by reading P4DDR.
  • Page 76: Addressing Modes And Effective Address Calculation

    Addressing Modes and Effective Address Calculation 2.7.1 Addressing Modes The H8/300H CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program- counter relative and memory indirect.
  • Page 77 4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn: • Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) the lower 24 bits of which contain the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents (32 bits) and the sum is stored in the address register.
  • Page 78: Effective Address Calculation

    extended to 24 bits and added to the 24-bit PC contents to generate a 24-bit branch address. The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes (–16383 to +16384 words) from the branch instruction.
  • Page 79 Table 2.13 Effective Address Calculation...
  • Page 82: Processing States

    Processing States 2.8.1 Overview The H8/300H CPU has five processing states: the program execution state, exception-handling state, power-down state, reset state, and bus-released state. The power-down state includes sleep mode, software standby mode, and hardware standby mode. Figure 2.11 classifies the processing states.
  • Page 83: Exception-Handling State

    2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from the exception vector table and branches to that address. In interrupt and trap exception handling the CPU references the stack pointer (ER7) and saves the program counter and condition code register.
  • Page 84: Exception Handling Operation

    Bus request End of bus release Program execution state End of bus SLEEP release instruction with SSBY = 0 request Exception handling source Bus-released state Sleep mode End of SLEEP instruction Interrupt source exception with SSBY = 1 handling NMI, IRQ , IRQ , or IRQ interrupt Exception-handling state Software standby mode...
  • Page 85: Bus-Released State

    Figure 2.14 shows the stack after the exception-handling sequence. SP–4 SP (ER7) SP–3 SP+1 SP–2 SP+2 SP–1 SP+3 Stack area SP (ER7) SP+4 Even address Before exception After exception Pushed on stack handling starts handling ends Legend: CCR: Condition code register Stack pointer Notes: 1.
  • Page 86: Power-Down State

    Figure 2.15 shows the on-chip memory access cycle. Figure 2.16 indicates the pin states. All H8/3062 Series models except the H8/3062F-ZTAT have a function for changing the method of outputting addresses from the address pins. For details see section 6.3.5, Address...
  • Page 87: On-Chip Supporting Module Access Timing

    Bus cycle T state T state φ Internal address bus Address Internal read signal Internal data bus Read data (read access) Internal write signal Internal data bus Write data (write access) Figure 2.15 On-Chip Memory Access Cycle φ Address bus Address RD HWR LWR High...
  • Page 88: Access To External Address Space

    Bus cycle T state T state T state φ Address Address bus Internal read signal Read access Internal data bus Read data Internal write signal Write access Internal data bus Write data Figure 2.17 Access Cycle for On-Chip Supporting Modules φ...
  • Page 89: Mcu Operating Modes

    3.1.1 Operating Mode Selection The H8/3062 Series has seven operating modes (modes 1 to 7) that are selected by the mode pins to MD ) as indicated in table 3.1. The input at these pins determines the size of the address space and the initial bus mode.
  • Page 90: Register Configuration

    64 kbytes. Mode 7 supports a maximum address space of 1 Mbyte. The H8/3062 Series can be used only in modes 1 to 7. The inputs at the mode pins must select one of these seven modes. The inputs at the mode pins must not be changed during operation. Set the reset state before changing the inputs at these pins.
  • Page 91: System Control Register (Syscr)

    Note: The versions with on-chip flash memory have a boot mode in which flash memory can be programmed. In boot mode, the MDS2 bit value is the inverse of the level at the MD2 pin. System Control Register (SYSCR) SYSCR is an 8-bit register that controls the operation of the H8/3062 Series. SSBY STS2...
  • Page 92 Bit 7—Software Standby (SSBY): Enables transition to software standby mode. (For further information about software standby mode see section 21, Power-Down State.) When software standby mode is exited by an external interrupt, and a transition is made to normal operation, this bit remains set to 1. To clear this bit, write 0. Bit 7 SSBY Description...
  • Page 93: Operating Mode Descriptions

    Bit 2—NMI Edge Select (NMIEG): Selects the valid edge of the NMI input. Bit 2 NMIEG Description An interrupt is requested at the falling edge of NMI (Initial value) An interrupt is requested at the rising edge of NMI Bit 1—Software Standby Output Port Enable (SSOE): Specifies whether the address bus and to CS , AS, RD, HWR, LWR) are kept as outputs or fixed high, or placed bus control signals (CS...
  • Page 94: Mode 3

    3.4.3 Mode 3 Ports 1, 2, and 5 and part of port A function as address pins A to A , permitting access to a maximum 16-Mbyte address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas.
  • Page 95: Pin Functions In Each Operating Mode

    Pin Functions in Each Operating Mode The pin functions of ports 1 to 5 and port A vary depending on the operating mode. Table 3.3 indicates their functions in each operating mode. Table 3.3 Pin Functions in Each Mode Port Mode 1 Mode 2 Mode 3...
  • Page 96: Memory Map In Each Operating Mode

    Comparison of H8/3062 Series Memory Maps In the H8/3062 Series, the address maps vary according to the size of the on-chip ROM and RAM. The internal I/O register space is the same in all models, and the H8/3062F-ZTAT A-mask version and H8/3062 have the same address map.
  • Page 97: Reserved Areas

    3.6.2 Reserved Areas The H8/3062 Series memory map includes reserved areas to which access (reading or writing) is prohibited. Normal operation cannot be guaranteed if the following reserved areas are accessed. Reserved Area in Internal I/O Register Space: The H8/3062 Series internal I/O register space includes a reserved area to which access is prohibited.
  • Page 98 (2) H'FFFFE9 H'FFFFEA External address space H'FFFFFF Note: * External addresses can be accessed by disabling on-chip RAM. Figure 3.1 Memory Map of H8/3062F-ZTAT, H8/3062F-ZTAT R-Mask Version, H8/3062F-ZTAT A-Mask Version, and H8/3062 Mask ROM Version in Each Operating Mode...
  • Page 99 H'FFFFE9 H'FFFFF H'FFFFEA External address space H'FFFFFF Note: * External addresses can be accessed by disabling on-chip RAM. Figure 3.1 Memory Map of H8/3062F-ZTAT, H8/3062F-ZTAT R-Mask Version, H8/3062F-ZTAT A-Mask Version, and H8/3062 Mask ROM Version in Each Operating Mode (cont)
  • Page 100 Modes 1 and 2 Modes 3 and 4 (1-Mbyte expanded modes with (16-Mbyte expanded modes with on-chip ROM disabled) on-chip ROM disabled) H'00000 H'000000 Vector area Vector area H'000FF H'0000FF H'007FFF H'07FFF Area 0 Area 0 H'1FFFF H'1FFFFF H'20000 Area 1 H'3FFFF H'200000 H'40000...
  • Page 101 Mode 5 Mode 6 Mode 7 (16-Mbyte expanded mode with (single-chip normal mode) (single-chip advanced mode) on-chip ROM enabled) H'000000 H'0000 H'00000 Vector area Vector area Vector area H'00FF H'000FF H'0000FF On-chip ROM On-chip ROM On-chip ROM (mask ROM) (mask ROM) (mask ROM) H'007FFF H'07FFF...
  • Page 102 Modes 1 and 2 Modes 3 and 4 (1-Mbyte expanded modes with (16-Mbyte expanded modes with on-chip ROM disabled) on-chip ROM disabled) H'00000 H'000000 Vector area Vector area H'000FF H'0000FF H'07FFF H'007FFF Area 0 Area 0 H'1FFFF H'1FFFFF H'20000 Area 1 H'3FFFF H'200000 H'40000...
  • Page 103 Mode 5 Mode 6 Mode 7 (16-Mbyte expanded mode with (single-chip normal mode) (single-chip advanced mode) on-chip ROM enabled) H'000000 H'0000 H'00000 Vector area Vector area Vector area H'0000FF H'000FF H'00FF On-chip ROM On-chip ROM On-chip ROM (mask ROM) (mask ROM) (mask ROM) H'007FFF H'07FFF...
  • Page 104 Modes 1 and 2 Modes 3 and 4 (1-Mbyte expanded modes with (16-Mbyte expanded modes with on-chip ROM disabled) on-chip ROM disabled) H'00000 H'000000 Vector area Vector area H'000FF H'0000FF H'07FFF H'007FFF Area 0 Area 0 H'1FFFF H'1FFFFF H'20000 Area 1 H'3FFFF H'200000 H'40000...
  • Page 105 Mode 5 Mode 6 Mode 7 (16-Mbyte expanded mode with (single-chip normal mode) (single-chip advanced mode) on-chip ROM enabled) H'000000 H'00000 H'0000 Vector area Vector area Vector area H'0000FF H'00FF H'000FF On-chip ROM On-chip ROM (flash memory) On-chip ROM (flash memory) (flash memory) H'007FFF H'07FFF...
  • Page 106: Exception Handling

    Section 4 Exception Handling Overview 4.1.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, interrupt, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in priority order.
  • Page 107: Exception Vector Table

    4.1.3 Exception Vector Table The exception sources are classified as shown in figure 4.1. Different vectors are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. • Reset External interrupts: NMI, IRQ to IRQ Exception •...
  • Page 108 Table 4.2 Exception Vector Table Vector Address* Exception Source Vector Number Advanced Mode Normal Mode Reset H'0000 to H'0003 H'0000 to H'0001 Reserved for system use H'0004 to H'0007 H'0002 to H'0003 H'0008 to H'000B H'0004 to H'0005 H'000C to H'000F H'0006 to H'0007 H'0010 to H'0013 H'0008 to H'0009...
  • Page 109: Reset

    Reset 4.2.1 Overview A reset is the highest-priority exception. When the RES pin goes low, all processing halts and the chip enters the reset state. A reset initializes the internal state of the CPU and the registers of the on-chip supporting modules. Reset exception handling begins when the RES pin changes from low to high.
  • Page 110 Figure 4.2 Reset Sequence (Modes 1 and 3)
  • Page 111 Internal Vector fetch processing Prefetch of first program instruction φ Address bus High to D (1), (3) Address of reset exception handling vector: (1) = H'000000, (3) = H'000002 (2), (4) Start address (contents of reset exception handling vector address) Start address First instruction of program Note: After a reset, the wait-state controller inserts three wait states in every bus cycle.
  • Page 112: Interrupts After Reset

    Prefetch of Internal first program processing Vector fetch instruction φ Internal address bus Internal read signal Internal write signal Internal data bus (16 bits wide) (1) Address of reset exception handling vector (H'0000) (2) Start address (contents of reset exception handling vector address) (3) First instruction of program Figure 4.4 Reset Sequence (Mode 6) 4.2.3...
  • Page 113: Interrupts

    Interrupts Interrupt exception handling can be requested by seven external sources (NMI, IRQ to IRQ ), and 27 internal sources in the on-chip supporting modules. Figure 4.5 classifies the interrupt sources and indicates the number of interrupts of each type. The on-chip supporting modules that can request interrupts are the watchdog timer (WDT), 16-bit timer, 8-bit timer, serial communication interface (SCI), and A/D converter.
  • Page 114: Stack Status After Exception Handling

    Stack Status after Exception Handling Figure 4.6 shows the stack after completion of trap instruction exception handling and interrupt exception handling. → SP–4 SP (ER7) SP–3 SP+1 SP–2 SP+2 SP–1 SP+3 SP (ER7) → Stack area SP+4 Even address Before exception handling After exception handling Pushed on stack a.
  • Page 115: Notes On Stack Usage

    Notes on Stack Usage When accessing word data or longword data, the H8/3062 Series regards the lowest address bit as 0. The stack should always be accessed by word access or longword access, and the value of the stack pointer (SP:ER7) should always be kept even.
  • Page 116 H'FFFEFA H'FFFEFB H'FFFEFC H'FFFEFD H'FFFEFE H'FFFEFF TRAPA instruction executed MOV. B R1L, @-ER7 SP set to H'FFFEFF Data saved above SP CCR contents lost Legend CCR: Condition code register Program counter R1L: General register R1L Stack pointer Note: The diagram illustrates modes 3 to 5. Figure 4.7 Operation when SP Value is Odd...
  • Page 117: Overview

    Section 5 Interrupt Controller Overview 5.1.1 Features The interrupt controller has the following features: • Interrupt priority registers (IPRs) for setting interrupt priorities Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis in interrupt priority registers A and B (IPRA and IPRB). •...
  • Page 118: Block Diagram

    5.1.2 Block Diagram Figure 5.1 shows a block diagram of the interrupt controller. ISCR IPRA, IPRB input IRQ input IRQ input section ISR Interrupt request Priority decision logic Vector number TEIE Interrupt controller SYSCR Legend: ISCR: IRQ sense control register IER: IRQ enable register ISR:...
  • Page 119: Pin Configuration

    5.1.3 Pin Configuration Table 5.1 lists the interrupt pins. Table 5.1 Interrupt Pins Name Abbreviation I/O Function Nonmaskable interrupt Input Nonmaskable interrupt*, rising edge or falling edge selectable to IRQ External interrupt request 5 to 0 Input Maskable interrupts, falling edge or level sensing selectable Note: * In the versions with on-chip flash memory, NMI input is sometimes disabled.
  • Page 120: Interrupt Priority Registers A And B (Ipra, Iprb)

    SYSCR is initialized to H'09 by a reset and in hardware standby mode. It is not initialized in software standby mode. SSBY STS2 STS1 STS0 NMIEG SSOE RAME Initial value Read/Write RAM enable Software standby output port enable NMI edge select Standby timer Selects the NMI input edge select 2 to 0...
  • Page 121 Interrupt Priority Register A (IPRA): IPRA is an 8-bit readable/writable register in which interrupt priority levels can be set. IPRA7 IPRA6 IPRA5 IPRA4 IPRA3 IPRA2 IPRA1 IPRA0 Initial value Read/Write Priority level A0 Selects the priority level of 16-bit timer channel 2 interrupt requests...
  • Page 122 Bit 7—Priority Level A7 (IPRA7): Selects the priority level of IRQ interrupt requests. Bit 7 IPRA7 Description interrupt requests have priority level 0 (low priority) (Initial value) interrupt requests have priority level 1 (high priority) Bit 6—Priority Level A6 (IPRA6): Selects the priority level of IRQ interrupt requests.
  • Page 123 Bit 2—Priority Level A2 (IPRA2): Selects the priority level of 16-bit timer channel 0 interrupt requests. Bit 2 IPRA2 Description 16-bit timer channel 0 interrupt requests have priority level 0 (low priority) (Initial value) 16-bit timer channel 0 interrupt requests have priority level 1 (high priority) Bit 1—Priority Level A1 (IPRA1): Selects the priority level of 16-bit timer channel 1 interrupt requests.
  • Page 124 Interrupt Priority Register B (IPRB): IPRB is an 8-bit readable/writable register in which interrupt priority levels can be set. IPRB7 IPRB6 — — IPRB3 IPRB2 — — Initial value Read/Write Reserved bit Priority level B2 Selects the priority level of SCI channel 1 interrupt requests Priority level B3 Selects the priority level of SCI...
  • Page 125: Irq Status Register (Isr)

    Bit 6—Priority Level B6 (IPRB6): Selects the priority level of 8-bit timer channel 2, 3 interrupt requests. Bit 6 IPRB6 Description 8-bit timer channel 2 and 3 interrupt requests have priority level 0 (low priority) (Initial value) 8-bit timer channel 2 and 3 interrupt requests have priority level 1 (high priority) Bits 5 and 4—Reserved: This bit can be written and read, but it does not affect interrupt priority.
  • Page 126: Irq Enable Register (Ier)

    — — IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial value Read/Write — — R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * Reserved bits IRQ to IRQ flags These bits indicate IRQ to IRQ flag interrupt request status Note: Only 0 can be written, to clear flags.
  • Page 127: Irq Sense Control Register (Iscr)

    Bits 7 and 6—Reserved: These bits can be written and read, but they do not enable or disable interrupts. Bits 5 to 0—IRQ to IRQ Enable (IRQ5E to IRQ0E): These bits enable or disable to IRQ interrupts. Bits 5 to 0 IRQ5E to IRQ0E Description to IRQ interrupts are disabled...
  • Page 128: Interrupt Sources

    Interrupt Sources The interrupt sources include external interrupts (NMI, IRQ to IRQ ) and 27 internal interrupts. 5.3.1 External Interrupts There are seven external interrupts: NMI, and IRQ to IRQ . Of these, NMI, IRQ , IRQ , and can be used to exit software standby mode. NMI: NMI is the highest-priority interrupt and is always accepted, regardless of the states of the I and UI bits in CCR*.
  • Page 129: Internal Interrupts

    Figure 5.3 shows the timing of the setting of the interrupt flags (IRQnF). φ IRQn input pin IRQnF Note: n = 5 to 0 Figure 5.3 Timing of Setting of IRQnF Interrupts IRQ to IRQ have vector numbers 12 to 17. These interrupts are detected regardless of whether the corresponding pin is set for input or output.
  • Page 130 Table 5.3 Interrupt Sources, Vector Addresses, and Priority Vector Address* Vector Interrupt Source Origin Number Advanced Mode Normal Mode Priority External H'001C to H'001F H'000E to H'000F — High pins H'0030 to H'0033 H'0018 to H'0019 IPRA7 H'0034 to H0037 H'001A to H'001B IPRA6 H'0038 to H'003B H'001C to H'001D...
  • Page 131 Vector Address* Vector Interrupt Source Origin Number Advanced Mode Normal Mode Priority IMIA2 16-bit timer H'0080 to H'0083 H'0040 to H'0041 IPRA0 High (compare match/ channel 2 input capture A2) IMIB2 H'0084 to H'0087 H'0042 to H'0043 (compare match/ input capture B2) OVI2 (overflow 2) H'0088 to H'008B H'0044 to H'0045...
  • Page 132 Vector Address* Vector Interrupt Source Origin Number Advanced Mode Normal Mode Priority ERI0 H'00D0 to H'00D3 H'0068 to H'0069 IPRB3 High (receive error 0) channel 0 RXI0 (receive H'00D4 to H'00D7 H'006A to H'006B data full 0) TXI0 (transmit H'00D8 to H'00DB H'006C to H'006D data empty 0) TEI0...
  • Page 133: Interrupt Operation

    5.4.1 Interrupt Handling Process The H8/3062 Series handles interrupts differently depending on the setting of the UE bit. When UE = 1, interrupts are controlled by the I bit. When UE = 0, interrupts are controlled by the I and UI bits.
  • Page 134 Program execution state Interrupt requested? Pending Priority level 1? TEI1 TEI1 I = 0 Save PC and CCR ← Read vector address Branch to interrupt service routine Figure 5.4 Process Up to Interrupt Acceptance when UE = 1...
  • Page 135 • If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. • When the interrupt controller receives one or more interrupt requests, it selects the highest- priority request, following the IPR interrupt priority settings, and holds other requests pending.
  • Page 136 ← All interrupts are Only NMI, IRQ , and ← ← 1, UI unmasked IRQ are unmasked Exception handling, ← ← or I 1, UI ← ← Exception handling, ← or UI All interrupts are masked except NMI Figure 5.5 Interrupt Masking State Transitions (Example) Figure 5.6 is a flowchart showing how interrupts are accepted when UE = 0.
  • Page 137 Program execution state Interrupt requested? Pending Priority level 1? TEI1 TEI1 I = 0 I = 0 UI = 0 Save PC and CCR ← ← 1, UI Read vector address Branch to interrupt service routine Figure 5.6 Process Up to Interrupt Acceptance when UE = 0...
  • Page 138: Interrupt Exception Handling Sequence

    5.4.2 Interrupt Exception Handling Sequence Figure 5.7 shows the interrupt exception handling sequence in mode 2 when the program code and stack are in an external memory area accessed in two states via a 16-bit bus. Figure 5.7 Interrupt Exception Handling Sequence...
  • Page 139: Interrupt Response Time

    5.4.3 Interrupt Response Time Table 5.5 indicates the interrupt response time from the occurrence of an interrupt request until the first instruction of the interrupt service routine is executed. Table 5.5 Interrupt Response Time External Memory 8-Bit Bus 16-Bit Bus On-Chip Item Memory...
  • Page 140: Usage Notes

    Usage Notes 5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction When an instruction clears an interrupt enable bit to 0 to disable the interrupt, the interrupt is not disabled until after execution of the instruction is completed. If an interrupt occurs while a BCLR, MOV, or other instruction is being executed to clear its interrupt enable bit to 0, at the instant when execution of the instruction ends the interrupt is still enabled, so its interrupt exception handling is carried out.
  • Page 141: Instructions That Inhibit Interrupts

    5.5.2 Instructions that Inhibit Interrupts The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs, after determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the CPU is currently executing one of these interrupt-inhibiting instructions, however, when the instruction is completed the CPU always continues by executing the next instruction.
  • Page 142: Bus Controller

    Section 6 Bus Controller Overview The H8/3062 Series has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily.
  • Page 143: Block Diagram

    6.1.2 Block Diagram Figure 6.1 shows a block diagram of the bus controller. to CS ABWCR ASTCR Area Internal address bus Internal signals CSCR decoder Chip select ADRCR Bus mode control signal control signals Bus size control signal Bus control circuit Access state control signal Wait request signal...
  • Page 144: Pin Configuration

    6.1.3 Pin Configuration Table 6.1 summarizes the input/output pins of the bus controller. Table 6.1 Bus Controller Pins Name Abbreviation Function to CS Chip select 0 to 7 Output Strobe signals selecting areas 0 to 7 Address strobe Output Strobe signal indicating valid address output on the address bus Read Output...
  • Page 145: Register Configuration

    6.1.4 Register Configuration Table 6.2 summarizes the bus controller’s registers. Table 6.2 Bus Controller Registers Address* Name Abbreviation Initial Value H'EE020 Bus width control register ABWCR H'FF* H'EE021 Access state control register ASTCR H'FF H'EE022 Wait control register H WCRH H'FF H'EE023 Wait control register L...
  • Page 146: Access State Control Register (Astcr)

    Bits 7 to 0—Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select 8-bit access or 16-bit access for the corresponding areas. Bits 7 to 0 ABW7 to ABW0 Description Areas 7 to 0 are 16-bit access areas Areas 7 to 0 are 8-bit access areas ABWCR specifies the data bus width of external memory areas.
  • Page 147: Wait Control Registers H And L (Wcrh, Wcrl)

    6.2.3 Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. On-chip memory and registers are accessed in a fixed number of states that does not depend on WCRH/WCRL settings.
  • Page 148 Bits 5 and 4—Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set to 1. Bit 5 Bit 4 Description Program wait not inserted when external space area 6 is accessed...
  • Page 149 WCRL Initial value Read/Write Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set to 1.
  • Page 150 Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1. Bit 3 Bit 2 Description Program wait not inserted when external space area 1 is accessed...
  • Page 151: Bus Release Control Register (Brcr)

    6.2.4 Bus Release Control Register (BRCR) BRCR is an 8-bit readable/writable register that enables address output on bus lines A to A enables or disables release of the bus to an external device. A23E A22E A21E A20E — — — BRLE Modes Initial value...
  • Page 152: Bus Control Register (Bcr)

    Bit 5—Address 21 Enable (A21E): Enables PA to be used as the A address output pin. Writing 0 in this bit enables A output from PA . In modes other than 3, 4, and 5, this bit cannot be modified and PA has its ordinary port functions.
  • Page 153 BCR is initialized to H'C6 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7—Idle Cycle Insertion 1 (ICIS1): Selects whether one idle cycle state is to be inserted between bus cycles in case of consecutive external read cycles for different areas. Bit 7 ICIS1 Description...
  • Page 154: Chip Select Control Register (Cscr)

    Bit 0—WAIT Pin Enable (WAITE): Enables or disables wait insertion by means of the WAIT pin. Bit 0 WAITE Description WAIT pin wait input is disabled, and the WAIT pin can be used as an input/output port (Initial value) WAIT pin wait input is enabled 6.2.6 Chip Select Control Register (CSCR) CSCR is an 8-bit readable/writable register that enables or disables output of chip select signals...
  • Page 155: Address Control Register (Adrcr)

    6.2.7 Address Control Register (ADRCR) ADRCR is an 8-bit readable/writable register that selects either address update mode 1 or address update mode 2 as the address output method. — — — — — — — ADRCTL Initial value Read/Write — —...
  • Page 156: Operation

    Operation 6.3.1 Area Division The external address space is divided into areas 0 to 7. Each area has a size of 128 kbytes in the 1- Mbyte modes, or 2 Mbytes in the 16-Mbyte modes. Figure 6.2 shows a general view of the memory map.
  • Page 157 (A) Memory map when RDEA = 1 (b) Memory map when RDEA = 0 Note: * Area 6 when the RAME bit is cleared. Figure 6.3 Memory Map in 16-Mbyte Mode (H8/3062F-ZTAT, H8/3062F-ZTAT A-Mask Version, H8/3062 Mask ROM Version, H8/3061 Mask ROM Version) (1)
  • Page 158 H'000000 Area 0 Area 0 2 Mbytes 2 Mbytes H'1FFFFF H'200000 Area 1 Area 1 2 Mbytes 2 Mbytes H'3FFFFF H'400000 Area 2 2 Mbytes Area 2 H'5FFFFF 8 Mbytes H'600000 Area 3 2 Mbytes H'7FFFFF H'800000 Area 4 2 Mbytes H'9FFFFF H'A00000 Area 5...
  • Page 159: Bus Specifications

    6.3.2 Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and registers are fixed, and are not affected by the bus controller.
  • Page 160: Memory Interfaces

    Chip Select Signals to CS For each of areas 0 to 7, the H8/3062 Series can output a chip select signal (CS ) that goes low when the corresponding area is selected in expanded mode. Figure 6.4 shows the output timing of a CSn signal.
  • Page 161: Address Output Method

    6.3.5 Address Output Method The H8/3062F-ZTAT R-mask version, H8/3062F-ZTAT A-mask version, H8/3062 mask ROM version, H8/3061 mask ROM version, H8/3060 mask ROM version, and H8/3064F-ZTAT provide a choice of two address update methods: either the same method as in the previous H8/300H Series (address update mode 1), or a method in which address updating is restricted to external space accesses (address update mode 2).
  • Page 162 H8/3062 mask ROM version, H8/3064F-ZTAT, or H8/3062F-ZTAT A-mask version. However, the following points should be noted. • ADRCR is allocated to address H'FEE01E. In the H8/3062F-ZTAT, the corresponding address is empty space, but it is necessary to confirm that no accesses are made to H'FEE01E in the program.
  • Page 163: Basic Bus Interface

    Basic Bus Interface 6.4.1 Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 6.3). 6.4.2 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (D to D...
  • Page 164: Valid Strobes

    In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd address.
  • Page 165: Memory Areas

    6.4.4 Memory Areas The initial state of each area is basic bus interface, three-state access space. The initial bus width is selected according to the operating mode. Area 0: Area 0 includes on-chip ROM, and in ROM-disabled expansion mode, all of area 0 is external space.
  • Page 166: Basic Bus Control Signal Timing

    6.4.5 Basic Bus Control Signal Timing 8-Bit, Three-State-Access Areas: Figure 6.9 shows the timing of bus control signals for an 8-bit, three-state-access area. The upper data bus (D to D ) is used in accesses to these areas. The LWR pin is always high. Wait states can be inserted. Bus cycle φ...
  • Page 167 8-Bit, Two-State-Access Areas: Figure 6.10 shows the timing of bus control signals for an 8-bit, ) is used in accesses to these areas. The LWR two-state-access area. The upper data bus (D to D pin is always high. Wait states cannot be inserted. Bus cycle φ...
  • Page 168 16-Bit, Three-State-Access Areas: Figures 6.11 to 6.13 show the timing of bus control signals for a 16-bit, three-state-access area. In these areas, the upper data bus (D to D ) is used in accesses to even addresses and the lower data bus (D to D ) in accesses to odd addresses.
  • Page 169 Bus cycle φ Address bus Odd external address in area n to D Invalid Read access to D Valid High Write access to D Undetermined data to D Valid Note: n = 7 to 0 Figure 6.12 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (2) (Byte Access to Odd Address)
  • Page 170 Bus cycle φ Address bus External address in area n Valid to D Read access to D Valid Write access Valid to D to D Valid Note: n = 7 to 0 Figure 6.13 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (3) (Word Access)
  • Page 171 16-Bit, Two-State-Access Areas: Figures 6.14 to 6.16 show the timing of bus control signals for a 16-bit, two-state-access area. In these areas, the upper data bus (D to D ) is used in accesses to even addresses and the lower data bus (D to D ) in accesses to odd addresses.
  • Page 172 Bus cycle φ Address bus Odd external address in area n to D Read access Invalid to D Valid High Write access to D Undetermined data to D Valid Note: n = 7 to 0 Figure 6.15 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (2) (Byte Access to Odd Address)