Page 1 Hitachi Single-Chip Microcomputer H8/3062 Series H8/3062 HD6433062 H8/3061 HD6433061 H8/3060 HD6433060 H8/3062F-ZTAT™ HD64F3062, HD64F3062R, HD64F3062A H8/3064F-ZTAT™ HD64F3064 Hardware Manual ADE-602-136B Rev. 3.0 3/20/00 Hitachi, Ltd.
Page 2 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.
Page 3 This version offers flexibility in the development of new products to meet fast-changing market needs. This manual describes the H8/3062 Series hardware. For details of the instruction set, refer to the H8/300H Series Programming Manual.
Page 4 Product code descriptions amended Table 1.1 Features CPU Description amended Figure 1.1 Block Diagram Notes amended Table 1.2 Comparison of H8/3062 Series Pin Added Arrangements Figure 1.4 Pin Arrangement of H8/3064F-ZTAT and Added H8/3062F-ZTAT A-Mask Version(FP-100B or TFP- 100B Package, Top View) Figure 1.5...
Page 5 Table 3.1 Operating Mode Selection Table amended 3.1.1 Operating Mode Selection Description added 3.4.5 Mode 5 Description added 3.6.1 Comparison of H8/3062 Series Memory Maps Added Figure 3.4 H8/3064F-ZTAT Memory Map in Each Added Operating Mode 80, 81 Figure 3.4 H8/3064F-ZTAT Memory Map in Each...
Page 6 20 MHz and 25 MHz added Frequencies (Smart Card Interface Mode) Figure 13.10 Procedure for Stopping and Restarting Amended the Clock 13.4 Usage Notes Description added 14.1 Overview Description added 14.1.1 Features High-speed conversion 25 MHz added Table 16.1 H8/3062 Series On-Chip RAM Added Specifications...
Page 7 17.9 Flash Memory Programming and Erasing 9 added Precautions 17.9 Flash Memory Programming and Erasing Note added Precautions Figure 17.19 ROM Block Diagram (H8/3062 Mask Amended ROM Version) 17.11 Notes on Ordering Mask ROM Version Chips 4 added 17.12 Notes when Converting the F-ZTAT Application...
Page 8 22.4 Electrical Characteristics of H8/3062F-ZTAT A- Added Mask Version Figure 22.19 Basic Bus Cycle: Three-State Access Amended with One Wait State Table B.1 Comparison of H8/3062 Series Internal I/O Table added Register Specifications 779 to B.2 Address List (H8/3064F-ZTAT) Table added 789 to B.3 Address List (H8/3062F-ZTAT A-Mask Version)
Page 9 There are seven members of the H8/3062 Series: the H8/3062F-ZTAT, H8/3062F-ZTAT R-mask version, H8/3062F-ZTAT A-mask version, and H8/3064F-ZTAT (all with on-chip flash memory), and the H8/3062 mask ROM version, H8/3061 mask ROM version, and H8/3060 mask ROM version. The specifications of these products are compared below.
Page 10 H8/3062 Mask ROM Version, H8/3061 Mask ROM Version, H8/3062F-ZTAT H8/3060 Mask H8/3062F-ZTAT H8/3062F-ZTAT R-Mask Version ROM Version H8/3064F-ZTAT A-Mask Version Address Compatible with Address update Address update Address update Address update output previous H8/300H mode 1 or 2 mode 1 or 2...
Page 11: Table Of Contents
Contents Section 1 Overview ......................Overview ..........................Block Diagram........................Pin Description ........................1.3.1 Pin Arrangement ....................1.3.2 Pin Functions......................12 1.3.3 Pin Assignments in Each Mode ................16 Notes on H8/3062F-ZTAT R-Mask Version ..............20 1.4.1 Pin Arrangement ....................20 1.4.2 Product Type Names and Markings..............
Page 12 Mode 6 ........................70 3.4.7 Mode 7 ........................70 Pin Functions in Each Operating Mode................71 Memory Map in Each Operating Mode................72 3.6.1 Comparison of H8/3062 Series Memory Maps ............ 72 3.6.2 Reserved Areas...................... 73 Section 4 Exception Handling ..................83 Overview ..........................
Page 13 4.2.2 Reset Sequence...................... 86 4.2.3 Interrupts after Reset ..................... 89 Interrupts ..........................90 Trap Instruction ........................90 Stack Status after Exception Handling ................91 Notes on Stack Usage......................92 Section 5 Interrupt Controller ..................95 Overview ..........................95 5.1.1 Features ......................... 95 5.1.2 Block Diagram ......................
Page 14 6.2.5 Bus Control Register (BCR) ................. 131 6.2.6 Chip Select Control Register (CSCR)..............133 6.2.7 Address Control Register (ADRCR)..............134 Operation ..........................135 6.3.1 Area Division ......................135 6.3.2 Bus Specifications ....................138 6.3.3 Memory Interfaces ....................139 6.3.4 Chip Select Signals....................139 6.3.5 Address Output Method ..................
Page 15 7.7.1 Overview ....................... 180 7.7.2 Register Descriptions .................... 181 Port 7 ..........................184 7.8.1 Overview ....................... 184 7.8.2 Register Description....................185 Port 8 ..........................186 7.9.1 Overview ....................... 186 7.9.2 Register Descriptions .................... 187 7.10 Port 9 ..........................191 7.10.1 Overview ....................... 191 7.10.2 Register Descriptions ....................
Page 16 8.4.4 PWM Mode ......................257 8.4.5 Phase Counting Mode ................... 261 8.4.6 16-Bit Timer Output Timing ................. 263 Interrupts ..........................264 8.5.1 Setting of Status Flags................... 264 8.5.2 Timing of Clearing of Status Flags ............... 266 8.5.3 Interrupt Sources ....................267 Usage Notes........................
Page 17 9.7.8 Contention between Compare Matches A and B ..........316 9.7.9 8TCNT Operation and Internal Clock Source Switchover ........316 Section 10 Programmable Timing Pattern Controller (TPC) ........319 10.1 Overview ..........................319 10.1.1 Features ......................... 319 10.1.2 Block Diagram ...................... 320 10.1.3 Pin Configuration ....................
Page 18 11.3.2 Interval Timer Operation ..................354 11.3.3 Timing of Setting of Overflow Flag (OVF)............354 11.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) ........355 11.4 Interrupts ..........................356 11.5 Usage Notes........................356 Section 12 Serial Communication Interface ..............
Page 19 13.3.2 Pin Connections ....................425 13.3.3 Data Format......................426 13.3.4 Register Settings....................428 13.3.5 Clock ........................430 13.3.6 Transmitting and Receiving Data................432 13.4 Usage Notes........................439 Section 14 A/D Converter ....................443 14.1 Overview ..........................443 14.1.1 Features ......................... 443 14.1.2 Block Diagram ......................
Page 20 17.8.2 Notes on Use of PROM Mode ................510 17.9 Flash Memory Programming and Erasing Precautions............511 17.10 Mask ROM (H8/3062 Mask ROM Version, H8/3061 Mask ROM Version, H8/3060 Mask ROM Version) Overview ................516 17.10.1 Block Diagram ...................... 516 17.11 Notes on Ordering Mask ROM Version Chips ..............
Page 21 18.2 Features ..........................521 18.2.1 Block Diagram ...................... 522 18.2.2 Pin Configuration ....................523 18.2.3 Register Configuration ..................523 18.3 Register Descriptions......................524 18.3.1 Flash Memory Control Register 1 (FLMCR1)............524 18.3.2 Flash Memory Control Register 2 (FLMCR2)............527 18.3.3 Erase Block Register 1 (EBR1) ................528 18.3.4 Erase Block Register 2 (EBR2) ................
Page 22 19.3.2 Flash Memory Control Register 2 (FLMCR2)............577 19.3.3 Erase Block Register (EBR).................. 578 19.3.4 RAM Control Register (RAMCR) ................ 579 19.4 Overview of Operation ....................... 581 19.4.1 Mode Transitions ....................581 19.4.2 On-Board Programming Modes................583 19.4.3 Flash Memory Emulation in RAM................ 585 19.4.4 Block Configuration....................
Page 23 21.7 System Clock Output Disabling Function................641 Section 22 Electrical Characteristics ................643 22.1 Electrical Characteristics of H8/3062 Mask ROM Version, H8/3061 Mask ROM Version, and H8/3060 Mask ROM Version........645 22.1.1 Absolute Maximum Ratings.................. 645 22.1.2 DC Characteristics ....................646 22.1.3 AC Characteristics ....................
Page 24 Number of States Required for Execution................759 Appendix B Internal I/O Registers ................. 768 Address List (H8/3062F-ZTAT, H8/3062F-ZTAT R-Mask Version, H8/3062 Mask ROM Version, H8/3061 Mask ROM Version, H8/3060 Mask ROM Version) ................... 769 Address List (H8/3064F-ZTAT) ..................779 Address List (H8/3062F-ZTAT A-Mask Version) ............789 Functions ..........................
Page 25 Appendix G Package Dimensions ................... 914 Appendix H Comparison of H8/300H Series Product Specifications ....917 Differences between H8/3067 and H8/3062 Series, H8/3048 Series, H8/3007 and H8/3006, and H8/3002.................. 917 Comparison of Pin Functions of 100-Pin Package Products (FP-100B, TFP-100B)..920...
Page 26: Section 1 Overview
(modes 1 to 7) include two single-chip modes and five expanded modes. In addition to its mask ROM versions, the H8/3062 Series has F-ZTAT™* versions with on-chip flash memory that allows programs to be freely rewritten by the user. This version enables users to respond quickly and flexibly to changing application specifications, growing production volumes, and other conditions.
Page 27 Multiply clock rate /subtract /divide H8/3062F-ZTZT 20 MHz 100 ns 700 ns H8/3062F-ZTAT R-Mask version H8/3062 (mask ROM version) H8/3061 (mask ROM version) H8/3060 (mask ROM version) H8/3064F-ZTAT 25 MHz 80 ns 560 ns H8/3062F-ZTAT A-Mask version 16-Mbyte address space Instruction features •...
Page 28 Feature Description • Bus controller Address space can be partitioned into eight areas, with independent bus specifications in each area • Chip select output available for areas 0 to 7 • 8-bit access or 16-bit access selectable for each area •...
Page 29 Feature Description • A/D converter Resolution: 10 bits • Eight channels, with selection of single or scan mode • Variable analog conversion voltage range • Sample-and-hold function • A/D conversion can be started by an external trigger or 8-bit timer compare- match •...
Page 30 Feature Description Product lineup Package Product Type Model (Hitachi Package Code) H8/3062F-ZTAT 5 V operation HD64F3062F 100-pin QFP (FP-100B) HD64F3062TE 100-pin TQFP (TFP-100B) HD64F3062FP 100-pin QFP (FP-100A) H8/3062F-ZTAT 5 V operation HD64F3062RF 100-pin QFP (FP-100B) R-mask version HD64F3062RTE 100-pin TQFP (TFP-100B)
Page 31: Block Diagram
Block Diagram Figure 1.1 shows an internal block diagram. Port 3 Port 4 Address bus P5 /A Data bus (upper) P5 /A P5 /A Data bus (lower) P5 /A EXTAL P2 /A XTAL P2 /A STBY H8/300H CPU P2 /A P2 /A RESO/FWE P2 /A...
Page 32: Pin Description
1.3.1 Pin Arrangement The pin arrangement of the H8/3062 Series is shown in figures 1.2 to 1.5. Differences in the H8/3062 Series pin arrangements are shown in table 1.2. The 5 V operation models of the H8/3064F-ZTAT and the H8/3062F-ZTAT A-mask version have a V pin.
Page 33 Note: * Functions as RESO in the mask ROM versions, and as FWE in the on-chip flash memory versions. Figure 1.2 Pin Arrangement of H8/3062F-ZTAT, H8/3062F-ZTAT R-Mask Version, H8/3062 Mask ROM Version, H8/3061 Mask ROM Version, and H8/3060 Mask ROM Version...
Page 34 Note: * Functions as RESO in the mask ROM versions, and as FWE in the on-chip flash memory versions. Figure 1.3 Pin Arrangement of H8/3062F-ZTAT, H8/3062F-ZTAT R-Mask Version, H8/3062 Mask ROM Version, H8/3061 Mask ROM Version, and H8/3060 Mask ROM Version...
Page 35 P7 /AN P7 /AN P7 /AN P7 /AN P7 /AN P7 /AN P7 /AN /DA P7 /AN /DA Top view /IRQ (FP-100B, TFP-100B) /IRQ ADTRG/CS /IRQ TCLKA/TP TCLKB/TP TCLKC/TIOCA TCLKD/TIOCB /TIOCA /TIOCB /TIOCA /TIOCB 0.1 µF Note: * V pin in 5 V operation models, V pin in 3 V operation models.
Page 36 Top view (FP-100A) /IRQ /IRQ /IRQ /IRQ /ADTRG /TCLKA D /P3 /TCLKB D /P3 /TIOCA /TCLKC D /P3 /TIOCB /TCLKD D /P3 /TIOCA D /P3 /TIOCB D /P3 0.1 µF Note: * V pin in 5 V operation models, V pin in 3 V operation models.
Page 37: Pin Functions
1.3.2 Pin Functions Table 1.3 summarizes the pin functions. The H8/3064F-ZTAT and the H8/3062F-ZTAT A-mask version 5 V operation models have a V pin, and require the connection of an external capacitor. Table 1.3 Pin Functions Pin No. FP-100B Type Symbol TFP-100B FP-100A I/O Name and Function...
Page 38 Pin No. FP-100B Type Symbol TFP-100B FP-100A I/O Name and Function System Input Reset input: When driven low, this pin resets control the chip. This pin must be driven low at power- RESO Output Reset output (On-chip mask ROM versions): Outputs the reset signal generated by the watchdog timer to external devices Input Write enable signal (On-chip flash memory...
Page 39 Pin No. FP-100B Type Symbol TFP-100B FP-100A I/O Name and Function 16-bit TCLKD to 96 to 93 98 to95 Input Clock input D to A: External clock inputs timer TCLKA TIOCA 99, 97, 95 1, 99, 97 Input/ Input capture/output compare A2 to A0: TIOCA output GRA2 to GRA0 output compare or input...
Page 40 B data direction register (PBDDR). Notes: 1. In the H8/3062F-ZTAT, H8/3062F-ZTAT R-mask version, H8/3062 mask ROM version, H8/3061 mask ROM version, and H8/3060 mask ROM version 2. In the H8/3064F-ZTAT and the H8/3062F-ZTAT A-mask version (5 V operation models).
Page 41: Pin Assignments In Each Mode
1.3.3 Pin Assignments in Each Mode Table 1.4 lists the pin assignments in each mode. Table 1.4 Pin Assignments in Each Mode (FP-100B or TFP-100B, FP-100A) Pin No. Pin Name FP-100B TFP-100B FP-100A Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7...
Page 42 Pin No. Pin Name FP-100B TFP-100B FP-100A Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 /WAIT /WAIT /WAIT /WAIT /WAIT...
Page 43 Pin No. Pin Name FP-100B TFP-100B FP-100A Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 /BREQ P6 /BREQ P6 /BREQ P6 /BREQ P6 /BREQ P6 /BACK P6 /BACK P6 /BACK P6 /BACK P6 /BACK P6 φ...
Page 44 Functions as the programming control signal in modes 5 and 7. 4. Functions as V in the H8/3062F-ZTAT, H8/3062F-ZTAT R-mask version, H8/3062 mask ROM version, H8/3061 mask ROM version, and H8/3060 mask ROM version. In the H8/3064F-ZTAT and the H8/3062F-ZTAT A-mask version, this pin functions as V in 5 V operation models, and as V in 3 V operation models.
Page 45: Notes On H8/3062F-Ztat R-Mask Version
Notes on H8/3062F-ZTAT R-Mask Version There are two models with on-chip flash memory in the H8/3062 Series: the H8/3062F-ZTAT (HD64F3062) and the H8/3062F-ZTAT R-mask version (HD64F3062R). Points to be noted when using the H8/3062F-ZTAT R-mask version are given below. 1.4.1...
Page 46: Product Type Names And Markings
Table 1.5 Differences in H8/3062F-ZTAT and H8/3062F-ZTAT R-Mask Version Markings H8/3062F-ZTAT H8/3062F-ZTAT R-Mask Version TFP-100 Product type name HD64F3062TE HD64F3062RTE Sample markings H8/3062 H8/3062 64F3062TE20 64F3062TE20 JAPAN JAPAN “R” is printed above the type name FP-100B Product type name HD64F3062F...
Page 47: Notes On H8/3064F-Ztat And H8/3062F-Ztat A-Mask Version
H8/3062F-ZTAT A-mask version are the same as for the H8/3062F-ZTAT R-mask version. Notes on H8/3064F-ZTAT and H8/3062F-ZTAT A-Mask Version The H8/3062 Series includes one model with 128-kbyte on-chip flash memory, the H8/3062F- ZTAT A-mask version (HD64F3062A) developed on the basis of the H8/3062F-ZTAT R-mask version, and one model with 256-kbyte large-capacity on-chip flash memory, the H8/3064F-ZTAT (HD64F3064).
Page 48: Product Type Names And Markings
Differences in H8/3062F-ZTAT R-Mask Version, H8/3062F-ZTAT A-Mask Version, and H8/3064F-ZTAT Markings H8/3062F-ZTAT H8/3062F-ZTAT R-Mask Version A-Mask Version H8/3064F-ZTAT TFP-100 Product type HD64F3062RTE HD64F3062ATE HD64F3064TE name Sample H8/3062 H8/3062 H8/3064 markings 64F3062TE20 64F3062TE20 64F3064TE20 JAPAN JAPAN JAPAN “A” is printed above the type name FP-100B Product type...
Page 49 (Connect the V power supply to other V pins as usual.) Note that the V output pin occupies the same location as a V pin in the H8/3062F-ZTAT R-mask version and on-chip mask ROM models (H8/3062, H8/3061, and H8/3060). power supply External capacitor 0.1 µF...
Page 50: Note On Changeover To Mask Rom Version
Note on Changeover to Mask ROM Version Care is required when changing from the H8/3062F-ZTAT A-mask version with on-chip flash memory to a model with on-chip mask ROM (H8/3062, H8/3061, or H8/3060). An external capacitor must be connected to the V pin of the H8/3062F-ZTAT A-mask version (5 V model).
Page 51: Setting Oscillation Settling Wait Time
Setting Oscillation Settling Wait Time When software standby mode is used, after exiting software standby mode a wait period must be provided to allow the clock to stabilize. Select the length of time for which the CPU and peripheral functions are to wait by setting bits STS2 to STS0 in the system control register (SYSCR) and bits DIV1 and DIV0 in the division ratio control register (DIVCR) according to the operating frequency of the chip.
Page 52: Cpu
 All frequently-used instructions execute in two to four states  Maximum clock frequency: 20 MHz (H8/3062F-ZTAT, H8/3062F-ZTAT R- Mask version, H8/3062, H8/3061, H8/3060) 25 MHz (H8/3064F-ZTAT, H8/3062F-ZTAT A- Mask version)  8/16/32-bit register-register add/subtract: 100 ns@20 MHz (80 ns@25 MHz) ...
Page 53: Differences From H8/300 Cpu
 16 ÷ 8-bit register-register divide: 700 ns@20 MHz (560 ns@25 MHz)  16 × 16-bit register-register multiply: 1.1 µs@20 MHz (0.88 µs@25 MHz)  32 ÷ 16-bit register-register divide: 1.1 µs@20 MHz (0.88 µs@25 MHz) • Two CPU operating modes ...
Page 54: Address Space
Address Space Figure 2.2 shows a simple memory map for the H8/3062 Series. The H8/300H CPU can address a linear address space with a maximum size of 64 kbytes in normal mode, and 16 Mbytes in advanced mode. For further details see section 3.6, Memory Map in Each Operating Mode.
Page 55: Register Configuration
Register Configuration 2.4.1 Overview The H8/300H CPU has the internal registers shown in figure 2.3. There are two types of registers: general registers and control registers. General Registers (ERn) (SP) Control Registers (CR) 6 5 4 3 2 1 0 I UI H U N Z V C Legend: Stack pointer...
Page 56: 2.4.2 General Registers
2.4.2 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used without distinction between data registers and address registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or as address registers, they are designated by the letters ER (ER0 to ER7).
Page 57: Control Registers
Free area SP (ER7) Stack area Figure 2.5 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC) and the 8-bit condition code register (CCR). Program Counter (PC): This 24-bit counter indicates the address of the next instruction the CPU will execute.
Page 58: Initial Cpu Register Values
Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0—Carry Flag (C): Set to 1 when a carry is generated by execution of an operation, and cleared to 0 otherwise. Used by: •...
Page 59: Data Formats
Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.
Page 60: Memory Data Formats
General Data Type Register Data Format Word data Word data Longword data Legend: ERn: General register General register E General register R MSB: Most significant bit LSB: Least significant bit Figure 2.7 General Register Data Formats 2.5.2 Memory Data Formats Figure 2.8 shows the data formats on memory.
Page 61 Data Type Address Data Format 1-bit data Address L Byte data Address L Word data Address 2M Address 2M + 1 Address 2N Longword data Address 2N + 1 Address 2N + 2 Address 2N + 3 Figure 2.8 Memory Data Formats When ER7 (SP) is used as an address register to access the stack, the operand size should be word size or longword size.
Page 62: Instruction Set
Notes: 1. POP.W Rn is identical to MOV.W @SP+, Rn. PUSH.W Rn is identical to MOV.W Rn, @–SP. POP.L ERn is identical to MOV.L @SP+, Rn. PUSH.L ERn is identical to MOV.L Rn, @–SP. 2. Not available in the H8/3062 Series. 3. Bcc is a generic branching instruction.
Page 63: Instructions And Addressing Modes
2.6.2 Instructions and Addressing Modes Table 2.2 indicates the instructions available in the H8/300H CPU. Table 2.2 Instructions and Addressing Modes Addressing Modes (d:16, (d:24, @ERn+/ (d:8, (d:16, Function Instruction @ERn ERn) ERn) @–ERn aa:8 aa:16 aa:24 aa:8 — Data —...
Page 64: Tables Of Instructions Classified By Function
2.6.3 Tables of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The operation notation used in these tables is defined next. Operation Notation General register (destination)* General register (source)* General register* General register (32-bit register or address register)* (EAd) Destination operand (EAs)
Page 65 Table 2.3 Data Transfer Instructions Instruction Size* Function (EAs) → Rd, Rs → (EAd) B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. (EAs) → Rd MOVFPE Cannot be used in this LSI.
Page 66 Table 2.4 Arithmetic Operation Instructions Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd ADD,SUB B/W/L Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from data in a general register.
Page 67 Instruction Size* Function Rd ÷ Rs → Rd DIVXU Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder Rd ÷...
Page 68 Table 2.5 Logic Operation Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd B/W/L Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd B/W/L Performs a logical OR operation on a general register and another general register or immediate data.
Page 69 Table 2.7 Bit Manipulation Instructions Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower 3 bits of a general register.
Page 70 Instruction Size* Function C ∨ (<bit-No.> of <EAd>) → C ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. C ∨...
Page 71 Table 2.8 Branching Instructions Instruction Size Function — Branches to a specified address if address specified condition is met. The branching conditions are listed below. Mnemonic Description Condition BRA (BT) Always (true) Always BRN (BF) Never (false) Never C ∨ Z = 0 High C ∨...
Page 72 Table 2.9 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling — Returns from an exception-handling routine SLEEP — Causes a transition to the power-down state (EAs) → CCR Moves the source operand contents to the condition code register. The condition code register size is one byte, but in transfer from memory, data is read by word access.
Page 73: 2.6.4 Basic Instruction Formats
Table 2.10 Block Transfer Instruction Instruction Size Function if R4L ≠ 0 then EEPMOV.B — @ER5+ → @ER6+, R4L – 1 → R4L repeat until R4L = 0 else next; if R4 ≠ 0 then EEPMOV.W — @ER5+ → @ER6+, R4 – 1 → R4 repeat until R4 = 0...
Page 74: Notes On Use Of Bit Manipulation Instructions
Operation field only NOP, RTS, etc. Operation field and register fields ADD.B Rn, Rm, etc. Operation field, register fields, and effective address extension MOV.B @(d:16, Rn), Rm EA (disp) Operation field, effective address extension, and condition field EA (disp) BRA d:8 Figure 2.9 Instruction Formats 2.6.5 Notes on Use of Bit Manipulation Instructions...
Page 75 Before Execution of BCLR Instruction Input/output Input Input Output Output Output Output Output Output Execution of BCLR Instruction BCLR #0, P4DDR Execute BCLR instruction on DDR After Execution of BCLR Instruction Input/output Output Output Output Output Output Output Output Input Explanation: To execute the BCLR instruction, the CPU begins by reading P4DDR.
Page 76: Addressing Modes And Effective Address Calculation
Addressing Modes and Effective Address Calculation 2.7.1 Addressing Modes The H8/300H CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program- counter relative and memory indirect.
Page 77 4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn: • Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) the lower 24 bits of which contain the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents (32 bits) and the sum is stored in the address register.
Page 78: Effective Address Calculation
extended to 24 bits and added to the 24-bit PC contents to generate a 24-bit branch address. The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes (–16383 to +16384 words) from the branch instruction.
Page 79 Table 2.13 Effective Address Calculation...
Page 82: Processing States
Processing States 2.8.1 Overview The H8/300H CPU has five processing states: the program execution state, exception-handling state, power-down state, reset state, and bus-released state. The power-down state includes sleep mode, software standby mode, and hardware standby mode. Figure 2.11 classifies the processing states.
Page 83: Exception-Handling State
2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from the exception vector table and branches to that address. In interrupt and trap exception handling the CPU references the stack pointer (ER7) and saves the program counter and condition code register.
Page 84: Exception Handling Operation
Bus request End of bus release Program execution state End of bus SLEEP release instruction with SSBY = 0 request Exception handling source Bus-released state Sleep mode End of SLEEP instruction Interrupt source exception with SSBY = 1 handling NMI, IRQ , IRQ , or IRQ interrupt Exception-handling state Software standby mode...
Page 85: Bus-Released State
Figure 2.14 shows the stack after the exception-handling sequence. SP–4 SP (ER7) SP–3 SP+1 SP–2 SP+2 SP–1 SP+3 Stack area SP (ER7) SP+4 Even address Before exception After exception Pushed on stack handling starts handling ends Legend: CCR: Condition code register Stack pointer Notes: 1.
Page 86: Power-Down State
Figure 2.15 shows the on-chip memory access cycle. Figure 2.16 indicates the pin states. All H8/3062 Series models except the H8/3062F-ZTAT have a function for changing the method of outputting addresses from the address pins. For details see section 6.3.5, Address...
Page 87: On-Chip Supporting Module Access Timing
Bus cycle T state T state φ Internal address bus Address Internal read signal Internal data bus Read data (read access) Internal write signal Internal data bus Write data (write access) Figure 2.15 On-Chip Memory Access Cycle φ Address bus Address RD HWR LWR High...
Page 88: Access To External Address Space
Bus cycle T state T state T state φ Address Address bus Internal read signal Read access Internal data bus Read data Internal write signal Write access Internal data bus Write data Figure 2.17 Access Cycle for On-Chip Supporting Modules φ...
Page 89: Mcu Operating Modes
3.1.1 Operating Mode Selection The H8/3062 Series has seven operating modes (modes 1 to 7) that are selected by the mode pins to MD ) as indicated in table 3.1. The input at these pins determines the size of the address space and the initial bus mode.
Page 90: Register Configuration
64 kbytes. Mode 7 supports a maximum address space of 1 Mbyte. The H8/3062 Series can be used only in modes 1 to 7. The inputs at the mode pins must select one of these seven modes. The inputs at the mode pins must not be changed during operation. Set the reset state before changing the inputs at these pins.
Page 91: System Control Register (Syscr)
Note: The versions with on-chip flash memory have a boot mode in which flash memory can be programmed. In boot mode, the MDS2 bit value is the inverse of the level at the MD2 pin. System Control Register (SYSCR) SYSCR is an 8-bit register that controls the operation of the H8/3062 Series. SSBY STS2...
Page 92 Bit 7—Software Standby (SSBY): Enables transition to software standby mode. (For further information about software standby mode see section 21, Power-Down State.) When software standby mode is exited by an external interrupt, and a transition is made to normal operation, this bit remains set to 1. To clear this bit, write 0. Bit 7 SSBY Description...
Page 93: Operating Mode Descriptions
Bit 2—NMI Edge Select (NMIEG): Selects the valid edge of the NMI input. Bit 2 NMIEG Description An interrupt is requested at the falling edge of NMI (Initial value) An interrupt is requested at the rising edge of NMI Bit 1—Software Standby Output Port Enable (SSOE): Specifies whether the address bus and to CS , AS, RD, HWR, LWR) are kept as outputs or fixed high, or placed bus control signals (CS...
Page 94: Mode 3
3.4.3 Mode 3 Ports 1, 2, and 5 and part of port A function as address pins A to A , permitting access to a maximum 16-Mbyte address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas.
Page 95: Pin Functions In Each Operating Mode
Pin Functions in Each Operating Mode The pin functions of ports 1 to 5 and port A vary depending on the operating mode. Table 3.3 indicates their functions in each operating mode. Table 3.3 Pin Functions in Each Mode Port Mode 1 Mode 2 Mode 3...
Page 96: Memory Map In Each Operating Mode
Comparison of H8/3062 Series Memory Maps In the H8/3062 Series, the address maps vary according to the size of the on-chip ROM and RAM. The internal I/O register space is the same in all models, and the H8/3062F-ZTAT A-mask version and H8/3062 have the same address map.
Page 97: Reserved Areas
3.6.2 Reserved Areas The H8/3062 Series memory map includes reserved areas to which access (reading or writing) is prohibited. Normal operation cannot be guaranteed if the following reserved areas are accessed. Reserved Area in Internal I/O Register Space: The H8/3062 Series internal I/O register space includes a reserved area to which access is prohibited.
Page 98 (2) H'FFFFE9 H'FFFFEA External address space H'FFFFFF Note: * External addresses can be accessed by disabling on-chip RAM. Figure 3.1 Memory Map of H8/3062F-ZTAT, H8/3062F-ZTAT R-Mask Version, H8/3062F-ZTAT A-Mask Version, and H8/3062 Mask ROM Version in Each Operating Mode...
Page 99 H'FFFFE9 H'FFFFF H'FFFFEA External address space H'FFFFFF Note: * External addresses can be accessed by disabling on-chip RAM. Figure 3.1 Memory Map of H8/3062F-ZTAT, H8/3062F-ZTAT R-Mask Version, H8/3062F-ZTAT A-Mask Version, and H8/3062 Mask ROM Version in Each Operating Mode (cont)
Page 100 Modes 1 and 2 Modes 3 and 4 (1-Mbyte expanded modes with (16-Mbyte expanded modes with on-chip ROM disabled) on-chip ROM disabled) H'00000 H'000000 Vector area Vector area H'000FF H'0000FF H'007FFF H'07FFF Area 0 Area 0 H'1FFFF H'1FFFFF H'20000 Area 1 H'3FFFF H'200000 H'40000...
Page 101 Mode 5 Mode 6 Mode 7 (16-Mbyte expanded mode with (single-chip normal mode) (single-chip advanced mode) on-chip ROM enabled) H'000000 H'0000 H'00000 Vector area Vector area Vector area H'00FF H'000FF H'0000FF On-chip ROM On-chip ROM On-chip ROM (mask ROM) (mask ROM) (mask ROM) H'007FFF H'07FFF...
Page 102 Modes 1 and 2 Modes 3 and 4 (1-Mbyte expanded modes with (16-Mbyte expanded modes with on-chip ROM disabled) on-chip ROM disabled) H'00000 H'000000 Vector area Vector area H'000FF H'0000FF H'07FFF H'007FFF Area 0 Area 0 H'1FFFF H'1FFFFF H'20000 Area 1 H'3FFFF H'200000 H'40000...
Page 103 Mode 5 Mode 6 Mode 7 (16-Mbyte expanded mode with (single-chip normal mode) (single-chip advanced mode) on-chip ROM enabled) H'000000 H'0000 H'00000 Vector area Vector area Vector area H'0000FF H'000FF H'00FF On-chip ROM On-chip ROM On-chip ROM (mask ROM) (mask ROM) (mask ROM) H'007FFF H'07FFF...
Page 104 Modes 1 and 2 Modes 3 and 4 (1-Mbyte expanded modes with (16-Mbyte expanded modes with on-chip ROM disabled) on-chip ROM disabled) H'00000 H'000000 Vector area Vector area H'000FF H'0000FF H'07FFF H'007FFF Area 0 Area 0 H'1FFFF H'1FFFFF H'20000 Area 1 H'3FFFF H'200000 H'40000...
Page 105 Mode 5 Mode 6 Mode 7 (16-Mbyte expanded mode with (single-chip normal mode) (single-chip advanced mode) on-chip ROM enabled) H'000000 H'00000 H'0000 Vector area Vector area Vector area H'0000FF H'00FF H'000FF On-chip ROM On-chip ROM (flash memory) On-chip ROM (flash memory) (flash memory) H'007FFF H'07FFF...
Page 106: Exception Handling
Section 4 Exception Handling Overview 4.1.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, interrupt, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in priority order.
Page 107: Exception Vector Table
4.1.3 Exception Vector Table The exception sources are classified as shown in figure 4.1. Different vectors are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. • Reset External interrupts: NMI, IRQ to IRQ Exception •...
Page 108 Table 4.2 Exception Vector Table Vector Address* Exception Source Vector Number Advanced Mode Normal Mode Reset H'0000 to H'0003 H'0000 to H'0001 Reserved for system use H'0004 to H'0007 H'0002 to H'0003 H'0008 to H'000B H'0004 to H'0005 H'000C to H'000F H'0006 to H'0007 H'0010 to H'0013 H'0008 to H'0009...
Page 109: Reset
Reset 4.2.1 Overview A reset is the highest-priority exception. When the RES pin goes low, all processing halts and the chip enters the reset state. A reset initializes the internal state of the CPU and the registers of the on-chip supporting modules. Reset exception handling begins when the RES pin changes from low to high.
Page 110 Figure 4.2 Reset Sequence (Modes 1 and 3)
Page 111 Internal Vector fetch processing Prefetch of first program instruction φ Address bus High to D (1), (3) Address of reset exception handling vector: (1) = H'000000, (3) = H'000002 (2), (4) Start address (contents of reset exception handling vector address) Start address First instruction of program Note: After a reset, the wait-state controller inserts three wait states in every bus cycle.
Page 112: Interrupts After Reset
Prefetch of Internal first program processing Vector fetch instruction φ Internal address bus Internal read signal Internal write signal Internal data bus (16 bits wide) (1) Address of reset exception handling vector (H'0000) (2) Start address (contents of reset exception handling vector address) (3) First instruction of program Figure 4.4 Reset Sequence (Mode 6) 4.2.3...
Page 113: Interrupts
Interrupts Interrupt exception handling can be requested by seven external sources (NMI, IRQ to IRQ ), and 27 internal sources in the on-chip supporting modules. Figure 4.5 classifies the interrupt sources and indicates the number of interrupts of each type. The on-chip supporting modules that can request interrupts are the watchdog timer (WDT), 16-bit timer, 8-bit timer, serial communication interface (SCI), and A/D converter.
Page 114: Stack Status After Exception Handling
Stack Status after Exception Handling Figure 4.6 shows the stack after completion of trap instruction exception handling and interrupt exception handling. → SP–4 SP (ER7) SP–3 SP+1 SP–2 SP+2 SP–1 SP+3 SP (ER7) → Stack area SP+4 Even address Before exception handling After exception handling Pushed on stack a.
Page 115: Notes On Stack Usage
Notes on Stack Usage When accessing word data or longword data, the H8/3062 Series regards the lowest address bit as 0. The stack should always be accessed by word access or longword access, and the value of the stack pointer (SP:ER7) should always be kept even.
Page 116 H'FFFEFA H'FFFEFB H'FFFEFC H'FFFEFD H'FFFEFE H'FFFEFF TRAPA instruction executed MOV. B R1L, @-ER7 SP set to H'FFFEFF Data saved above SP CCR contents lost Legend CCR: Condition code register Program counter R1L: General register R1L Stack pointer Note: The diagram illustrates modes 3 to 5. Figure 4.7 Operation when SP Value is Odd...
Page 117: Overview
Section 5 Interrupt Controller Overview 5.1.1 Features The interrupt controller has the following features: • Interrupt priority registers (IPRs) for setting interrupt priorities Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis in interrupt priority registers A and B (IPRA and IPRB). •...
Page 118: Block Diagram
5.1.2 Block Diagram Figure 5.1 shows a block diagram of the interrupt controller. ISCR IPRA, IPRB input IRQ input IRQ input section ISR Interrupt request Priority decision logic Vector number TEIE Interrupt controller SYSCR Legend: ISCR: IRQ sense control register IER: IRQ enable register ISR:...
Page 119: Pin Configuration
5.1.3 Pin Configuration Table 5.1 lists the interrupt pins. Table 5.1 Interrupt Pins Name Abbreviation I/O Function Nonmaskable interrupt Input Nonmaskable interrupt*, rising edge or falling edge selectable to IRQ External interrupt request 5 to 0 Input Maskable interrupts, falling edge or level sensing selectable Note: * In the versions with on-chip flash memory, NMI input is sometimes disabled.
Page 120: Interrupt Priority Registers A And B (Ipra, Iprb)
SYSCR is initialized to H'09 by a reset and in hardware standby mode. It is not initialized in software standby mode. SSBY STS2 STS1 STS0 NMIEG SSOE RAME Initial value Read/Write RAM enable Software standby output port enable NMI edge select Standby timer Selects the NMI input edge select 2 to 0...
Page 121 Interrupt Priority Register A (IPRA): IPRA is an 8-bit readable/writable register in which interrupt priority levels can be set. IPRA7 IPRA6 IPRA5 IPRA4 IPRA3 IPRA2 IPRA1 IPRA0 Initial value Read/Write Priority level A0 Selects the priority level of 16-bit timer channel 2 interrupt requests...
Page 122 Bit 7—Priority Level A7 (IPRA7): Selects the priority level of IRQ interrupt requests. Bit 7 IPRA7 Description interrupt requests have priority level 0 (low priority) (Initial value) interrupt requests have priority level 1 (high priority) Bit 6—Priority Level A6 (IPRA6): Selects the priority level of IRQ interrupt requests.
Page 123 Bit 2—Priority Level A2 (IPRA2): Selects the priority level of 16-bit timer channel 0 interrupt requests. Bit 2 IPRA2 Description 16-bit timer channel 0 interrupt requests have priority level 0 (low priority) (Initial value) 16-bit timer channel 0 interrupt requests have priority level 1 (high priority) Bit 1—Priority Level A1 (IPRA1): Selects the priority level of 16-bit timer channel 1 interrupt requests.
Page 124 Interrupt Priority Register B (IPRB): IPRB is an 8-bit readable/writable register in which interrupt priority levels can be set. IPRB7 IPRB6 — — IPRB3 IPRB2 — — Initial value Read/Write Reserved bit Priority level B2 Selects the priority level of SCI channel 1 interrupt requests Priority level B3 Selects the priority level of SCI...
Page 125: Irq Status Register (Isr)
Bit 6—Priority Level B6 (IPRB6): Selects the priority level of 8-bit timer channel 2, 3 interrupt requests. Bit 6 IPRB6 Description 8-bit timer channel 2 and 3 interrupt requests have priority level 0 (low priority) (Initial value) 8-bit timer channel 2 and 3 interrupt requests have priority level 1 (high priority) Bits 5 and 4—Reserved: This bit can be written and read, but it does not affect interrupt priority.
Page 126: Irq Enable Register (Ier)
— — IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial value Read/Write — — R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * Reserved bits IRQ to IRQ flags These bits indicate IRQ to IRQ flag interrupt request status Note: Only 0 can be written, to clear flags.
Page 127: Irq Sense Control Register (Iscr)
Bits 7 and 6—Reserved: These bits can be written and read, but they do not enable or disable interrupts. Bits 5 to 0—IRQ to IRQ Enable (IRQ5E to IRQ0E): These bits enable or disable to IRQ interrupts. Bits 5 to 0 IRQ5E to IRQ0E Description to IRQ interrupts are disabled...
Page 128: Interrupt Sources
Interrupt Sources The interrupt sources include external interrupts (NMI, IRQ to IRQ ) and 27 internal interrupts. 5.3.1 External Interrupts There are seven external interrupts: NMI, and IRQ to IRQ . Of these, NMI, IRQ , IRQ , and can be used to exit software standby mode. NMI: NMI is the highest-priority interrupt and is always accepted, regardless of the states of the I and UI bits in CCR*.
Page 129: Internal Interrupts
Figure 5.3 shows the timing of the setting of the interrupt flags (IRQnF). φ IRQn input pin IRQnF Note: n = 5 to 0 Figure 5.3 Timing of Setting of IRQnF Interrupts IRQ to IRQ have vector numbers 12 to 17. These interrupts are detected regardless of whether the corresponding pin is set for input or output.
Page 130 Table 5.3 Interrupt Sources, Vector Addresses, and Priority Vector Address* Vector Interrupt Source Origin Number Advanced Mode Normal Mode Priority External H'001C to H'001F H'000E to H'000F — High pins H'0030 to H'0033 H'0018 to H'0019 IPRA7 H'0034 to H0037 H'001A to H'001B IPRA6 H'0038 to H'003B H'001C to H'001D...
Page 131 Vector Address* Vector Interrupt Source Origin Number Advanced Mode Normal Mode Priority IMIA2 16-bit timer H'0080 to H'0083 H'0040 to H'0041 IPRA0 High (compare match/ channel 2 input capture A2) IMIB2 H'0084 to H'0087 H'0042 to H'0043 (compare match/ input capture B2) OVI2 (overflow 2) H'0088 to H'008B H'0044 to H'0045...
Page 132 Vector Address* Vector Interrupt Source Origin Number Advanced Mode Normal Mode Priority ERI0 H'00D0 to H'00D3 H'0068 to H'0069 IPRB3 High (receive error 0) channel 0 RXI0 (receive H'00D4 to H'00D7 H'006A to H'006B data full 0) TXI0 (transmit H'00D8 to H'00DB H'006C to H'006D data empty 0) TEI0...
Page 133: Interrupt Operation
5.4.1 Interrupt Handling Process The H8/3062 Series handles interrupts differently depending on the setting of the UE bit. When UE = 1, interrupts are controlled by the I bit. When UE = 0, interrupts are controlled by the I and UI bits.
Page 134 Program execution state Interrupt requested? Pending Priority level 1? TEI1 TEI1 I = 0 Save PC and CCR ← Read vector address Branch to interrupt service routine Figure 5.4 Process Up to Interrupt Acceptance when UE = 1...
Page 135 • If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. • When the interrupt controller receives one or more interrupt requests, it selects the highest- priority request, following the IPR interrupt priority settings, and holds other requests pending.
Page 136 ← All interrupts are Only NMI, IRQ , and ← ← 1, UI unmasked IRQ are unmasked Exception handling, ← ← or I 1, UI ← ← Exception handling, ← or UI All interrupts are masked except NMI Figure 5.5 Interrupt Masking State Transitions (Example) Figure 5.6 is a flowchart showing how interrupts are accepted when UE = 0.
Page 137 Program execution state Interrupt requested? Pending Priority level 1? TEI1 TEI1 I = 0 I = 0 UI = 0 Save PC and CCR ← ← 1, UI Read vector address Branch to interrupt service routine Figure 5.6 Process Up to Interrupt Acceptance when UE = 0...
Page 138: Interrupt Exception Handling Sequence
5.4.2 Interrupt Exception Handling Sequence Figure 5.7 shows the interrupt exception handling sequence in mode 2 when the program code and stack are in an external memory area accessed in two states via a 16-bit bus. Figure 5.7 Interrupt Exception Handling Sequence...
Page 139: Interrupt Response Time
5.4.3 Interrupt Response Time Table 5.5 indicates the interrupt response time from the occurrence of an interrupt request until the first instruction of the interrupt service routine is executed. Table 5.5 Interrupt Response Time External Memory 8-Bit Bus 16-Bit Bus On-Chip Item Memory...
Page 140: Usage Notes
Usage Notes 5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction When an instruction clears an interrupt enable bit to 0 to disable the interrupt, the interrupt is not disabled until after execution of the instruction is completed. If an interrupt occurs while a BCLR, MOV, or other instruction is being executed to clear its interrupt enable bit to 0, at the instant when execution of the instruction ends the interrupt is still enabled, so its interrupt exception handling is carried out.
Page 141: Instructions That Inhibit Interrupts
5.5.2 Instructions that Inhibit Interrupts The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs, after determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the CPU is currently executing one of these interrupt-inhibiting instructions, however, when the instruction is completed the CPU always continues by executing the next instruction.
Page 142: Bus Controller
Section 6 Bus Controller Overview The H8/3062 Series has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily.
Page 143: Block Diagram
6.1.2 Block Diagram Figure 6.1 shows a block diagram of the bus controller. to CS ABWCR ASTCR Area Internal address bus Internal signals CSCR decoder Chip select ADRCR Bus mode control signal control signals Bus size control signal Bus control circuit Access state control signal Wait request signal...
Page 144: Pin Configuration
6.1.3 Pin Configuration Table 6.1 summarizes the input/output pins of the bus controller. Table 6.1 Bus Controller Pins Name Abbreviation Function to CS Chip select 0 to 7 Output Strobe signals selecting areas 0 to 7 Address strobe Output Strobe signal indicating valid address output on the address bus Read Output...
Page 145: Register Configuration
6.1.4 Register Configuration Table 6.2 summarizes the bus controller’s registers. Table 6.2 Bus Controller Registers Address* Name Abbreviation Initial Value H'EE020 Bus width control register ABWCR H'FF* H'EE021 Access state control register ASTCR H'FF H'EE022 Wait control register H WCRH H'FF H'EE023 Wait control register L...
Page 146: Access State Control Register (Astcr)
Bits 7 to 0—Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select 8-bit access or 16-bit access for the corresponding areas. Bits 7 to 0 ABW7 to ABW0 Description Areas 7 to 0 are 16-bit access areas Areas 7 to 0 are 8-bit access areas ABWCR specifies the data bus width of external memory areas.
Page 147: Wait Control Registers H And L (Wcrh, Wcrl)
6.2.3 Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. On-chip memory and registers are accessed in a fixed number of states that does not depend on WCRH/WCRL settings.
Page 148 Bits 5 and 4—Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set to 1. Bit 5 Bit 4 Description Program wait not inserted when external space area 6 is accessed...
Page 149 WCRL Initial value Read/Write Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set to 1.
Page 150 Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1. Bit 3 Bit 2 Description Program wait not inserted when external space area 1 is accessed...
Page 151: Bus Release Control Register (Brcr)
6.2.4 Bus Release Control Register (BRCR) BRCR is an 8-bit readable/writable register that enables address output on bus lines A to A enables or disables release of the bus to an external device. A23E A22E A21E A20E — — — BRLE Modes Initial value...
Page 152: Bus Control Register (Bcr)
Bit 5—Address 21 Enable (A21E): Enables PA to be used as the A address output pin. Writing 0 in this bit enables A output from PA . In modes other than 3, 4, and 5, this bit cannot be modified and PA has its ordinary port functions.
Page 153 BCR is initialized to H'C6 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7—Idle Cycle Insertion 1 (ICIS1): Selects whether one idle cycle state is to be inserted between bus cycles in case of consecutive external read cycles for different areas. Bit 7 ICIS1 Description...
Page 154: Chip Select Control Register (Cscr)
Bit 0—WAIT Pin Enable (WAITE): Enables or disables wait insertion by means of the WAIT pin. Bit 0 WAITE Description WAIT pin wait input is disabled, and the WAIT pin can be used as an input/output port (Initial value) WAIT pin wait input is enabled 6.2.6 Chip Select Control Register (CSCR) CSCR is an 8-bit readable/writable register that enables or disables output of chip select signals...
Page 155: Address Control Register (Adrcr)
6.2.7 Address Control Register (ADRCR) ADRCR is an 8-bit readable/writable register that selects either address update mode 1 or address update mode 2 as the address output method. — — — — — — — ADRCTL Initial value Read/Write — —...
Page 156: Operation
Operation 6.3.1 Area Division The external address space is divided into areas 0 to 7. Each area has a size of 128 kbytes in the 1- Mbyte modes, or 2 Mbytes in the 16-Mbyte modes. Figure 6.2 shows a general view of the memory map.
Page 157 (A) Memory map when RDEA = 1 (b) Memory map when RDEA = 0 Note: * Area 6 when the RAME bit is cleared. Figure 6.3 Memory Map in 16-Mbyte Mode (H8/3062F-ZTAT, H8/3062F-ZTAT A-Mask Version, H8/3062 Mask ROM Version, H8/3061 Mask ROM Version) (1)
Page 158 H'000000 Area 0 Area 0 2 Mbytes 2 Mbytes H'1FFFFF H'200000 Area 1 Area 1 2 Mbytes 2 Mbytes H'3FFFFF H'400000 Area 2 2 Mbytes Area 2 H'5FFFFF 8 Mbytes H'600000 Area 3 2 Mbytes H'7FFFFF H'800000 Area 4 2 Mbytes H'9FFFFF H'A00000 Area 5...
Page 159: Bus Specifications
6.3.2 Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and registers are fixed, and are not affected by the bus controller.
Page 160: Memory Interfaces
Chip Select Signals to CS For each of areas 0 to 7, the H8/3062 Series can output a chip select signal (CS ) that goes low when the corresponding area is selected in expanded mode. Figure 6.4 shows the output timing of a CSn signal.
Page 161: Address Output Method
6.3.5 Address Output Method The H8/3062F-ZTAT R-mask version, H8/3062F-ZTAT A-mask version, H8/3062 mask ROM version, H8/3061 mask ROM version, H8/3060 mask ROM version, and H8/3064F-ZTAT provide a choice of two address update methods: either the same method as in the previous H8/300H Series (address update mode 1), or a method in which address updating is restricted to external space accesses (address update mode 2).
Page 162 H8/3062 mask ROM version, H8/3064F-ZTAT, or H8/3062F-ZTAT A-mask version. However, the following points should be noted. • ADRCR is allocated to address H'FEE01E. In the H8/3062F-ZTAT, the corresponding address is empty space, but it is necessary to confirm that no accesses are made to H'FEE01E in the program.
Page 163: Basic Bus Interface
Basic Bus Interface 6.4.1 Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 6.3). 6.4.2 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (D to D...
Page 164: Valid Strobes
In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd address.
Page 165: Memory Areas
6.4.4 Memory Areas The initial state of each area is basic bus interface, three-state access space. The initial bus width is selected according to the operating mode. Area 0: Area 0 includes on-chip ROM, and in ROM-disabled expansion mode, all of area 0 is external space.
Page 166: Basic Bus Control Signal Timing
6.4.5 Basic Bus Control Signal Timing 8-Bit, Three-State-Access Areas: Figure 6.9 shows the timing of bus control signals for an 8-bit, three-state-access area. The upper data bus (D to D ) is used in accesses to these areas. The LWR pin is always high. Wait states can be inserted. Bus cycle φ...
Page 167 8-Bit, Two-State-Access Areas: Figure 6.10 shows the timing of bus control signals for an 8-bit, ) is used in accesses to these areas. The LWR two-state-access area. The upper data bus (D to D pin is always high. Wait states cannot be inserted. Bus cycle φ...
Page 168 16-Bit, Three-State-Access Areas: Figures 6.11 to 6.13 show the timing of bus control signals for a 16-bit, three-state-access area. In these areas, the upper data bus (D to D ) is used in accesses to even addresses and the lower data bus (D to D ) in accesses to odd addresses.
Page 169 Bus cycle φ Address bus Odd external address in area n to D Invalid Read access to D Valid High Write access to D Undetermined data to D Valid Note: n = 7 to 0 Figure 6.12 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (2) (Byte Access to Odd Address)
Page 170 Bus cycle φ Address bus External address in area n Valid to D Read access to D Valid Write access Valid to D to D Valid Note: n = 7 to 0 Figure 6.13 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (3) (Word Access)
Page 171 16-Bit, Two-State-Access Areas: Figures 6.14 to 6.16 show the timing of bus control signals for a 16-bit, two-state-access area. In these areas, the upper data bus (D to D ) is used in accesses to even addresses and the lower data bus (D to D ) in accesses to odd addresses.
Page 172 Bus cycle φ Address bus Odd external address in area n to D Read access Invalid to D Valid High Write access to D Undetermined data to D Valid Note: n = 7 to 0 Figure 6.15 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (2) (Byte Access to Odd Address)
Page 173: Wait Control
(Word Access) 6.4.6 Wait Control When accessing external space, the H8/3062 Series can extend the bus cycle by inserting wait states (T ). There are two ways of inserting wait states: program wait insertion and pin wait insertion using the WAIT pin.
Page 174 Pin Wait Insertion: Setting the WAITE bit in BCR to 1 enables wait insertion by means of the WAIT pin. When external space is accessed in this state, a program wait is first inserted. If the WAIT pin is low at the falling edge of φ in the last T or T state, another T state is inserted.
Page 175: Idle Cycle
6.5.1 Operation When the H8/3062 Series chip accesses external space, it can insert a 1-state idle cycle (T between bus cycles in the following cases: when read accesses between different areas occur consecutively, and when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, which has a long output floating time, and high-speed memory, I/O interfaces, and so on.
Page 176 Bus cycle A Bus cycle B Bus cycle A Bus cycle B φ φ Address bus Address bus Data bus Data bus Data collision Long buffer-off time (a) Idle cycle not inserted (b) Idle cycle inserted Figure 6.19 Example of Idle Cycle Operation (ICIS0 = 1) Usage Note: When non-insertion of an idle cycle is specified, the rise (negation) of RD and fall (assertion) of CS may occur simultaneously.
Page 177: Pin States In Idle Cycle
6.5.2 Pin States in Idle Cycle Table 6.5 shows the pin states in an idle cycle. Table 6.5 Pin States in Idle Cycle Pins Pin State to A Next cycle address value to D High impedance High High High High High Bus Arbiter The bus controller has a built-in bus arbiter that arbitrates between different bus masters.
Page 178: Operation
BREQ signal goes high. While the bus is released to an external bus master, the H8/3062 Series chip holds the address bus, data bus, bus control signals (AS, RD, HWR, and LWR), and chip select signals (CSn: n = 7 to 0) in the high-impedance state, and holds the BACK pin in the low output state.
Page 179 CPU cycles External bus released CPU cycles φ High-impedance Address Address bus High-impedance Data bus High-impedance High-impedance High High-impedance HWR, LWR BREQ BACK Minimum 3 cycles Figure 6.21 Example of External Bus Master Operation When making a transition to software standby mode, if there is contention with a bus request from an external bus master, the BACK and strobe states may be indefinite when the transition is made.
Page 180: Register And Pin Input Timing
Register and Pin Input Timing 6.7.1 Register Write Timing ABWCR, ASTCR, WCRH, and WCRL Write Timing: Data written to ABWCR, ASTCR, WCRH, and WCRL takes effect starting from the next bus cycle. Figure 6.22 shows the timing when an instruction fetched from area 0 changes area 0 from three-state access to two-state access. φ...
Page 181: Breq Pin Input Timing
φ Address bus BRCR address to PA to A High-impedance Figure 6.24 BRCR Write Timing BREQ Pin Input Timing 6.7.2 After driving the BREQ pin low, hold it low until BACK goes low. If BREQ returns to the high level before BACK goes lows, the bus arbiter may operate incorrectly. To terminate the external-bus-released state, hold the BREQ signal high for at least three states.
Page 182: I/O Ports
Overview The H8/3062 Series has 10 input/output ports (ports 1, 2, 3, 4, 5, 6, 8, 9, A, and B) and one input- only port (port 7). Table 7.1 summarizes the port functions. The pins in each port are multiplexed as shown in table 7.1.
Page 183 Single-Chip Expanded Modes Modes Port Description Pins Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 Port 4 • 8-bit I/O to P4 Data input/output (D to D ) and 8-bit generic Generic input/ port to D input/output output...
Page 184 Single-Chip Expanded Modes Modes Port Description Pins Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 Port 8 • 5-bit I/O and IRQ input, CS and CS and IRQ /IRQ output, and generic port input input and generic input/output •...
Page 185 Single-Chip Expanded Modes Modes Port Description Pins Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 Port B • 8-bit I/O TPC output (TP to TP ) and generic input/output port TPC output (TP to TP ), 8-bit timer input and output TPC output (TP ), CS...
Page 186: Port 1
Port 1 7.2.1 Overview Port 1 is an 8-bit input/output port also used for address output, with the pin configuration shown in figure 7.1. The pin functions differ according to the operating mode. In modes 1 to 4 (expanded modes with on-chip ROM disabled), they are address bus output pins (A to A In mode 5 (expanded modes with on-chip ROM enabled), settings in the port 1 data direction register (P1DDR) can designate pins for address bus output (A...
Page 187 Port 1 Data Direction Register (P1DDR): P1DDR is an 8-bit write-only register that can select input or output for each pin in port 1. P1 DDR P1 DDR P1 DDR P1 DDR P1 DDR P1 DDR P1 DDR P1 DDR Initial value Modes 1 to 4...
Page 188 Port 1 Data Register (P1DR): P1DR is an 8-bit readable/writable register that stores port 1 output data. When port 1 functions as an output port, the value of this register is output. When this register is read, the pin logic level is read for bits for which the P1DDR setting is 0, and the P1DR value is read for bits for which the P1DDR setting is 1.
Page 189: Port 2
Port 2 7.3.1 Overview Port 2 is an 8-bit input/output port which also has an address output function. It’s pin configuration is shown in figure 7.2. The pin functions differ according to the operating mode. In modes 1 to 4 (expanded modes with on-chip ROM disabled), port 2 consists of address bus output pins (A to A ).
Page 190: Register Descriptions
7.3.2 Register Descriptions Table 7.3 summarizes the registers of port 2. Table 7.3 Port 2 Registers Initial Value Address* Name Abbreviation R/W Modes 1 to 4 Modes 5 to 7 H'EE001 Port 2 data direction register P2DDR H'FF H'00 H'FFFD1 Port 2 data register P2DR R/W H'00...
Page 191 In modes 5 to 7, P2DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P2DDR is initialized to H'FF in modes 1 to 4, and to H'00 in modes 5 to 7, by a reset and in hardware standby mode.
Page 192 Table 7.4 summarizes the states of the input pull-ups in each mode. Table 7.4 Input Pull-Up Transistor States (Port 2) Hardware Software Mode Reset Standby Mode Standby Mode Other Modes On/off On/off Legend Off: The input pull-up transistor is always off. On/off: The input pull-up transistor is on if P2PCR = 1 and P2DDR = 0.
Page 193: Port 3
Port 3 7.4.1 Overview Port 3 is an 8-bit input/output port which also functions as a data bus. It’s pin configuration is shown in figure 7.3. Port 3 is a data bus in modes 1 to 5 (expanded modes) and a generic input/output port in modes 6 and 7 (single-chip mode).
Page 194 Port 3 Data Direction Register (P3DDR): P3DDR is an 8-bit write-only register that can select input or output for each pin in port 3. P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR Initial value Read/Write Port 3 data direction 7 to 0...
Page 195: Overview
Port 4 7.5.1 Overview Port 4 is an 8-bit input/output port which also functions as a data bus. It’s pin configuration is shown in figure 7.4. The pin functions differ depending on the operating mode. In modes 1 to 5 (expanded modes), when the bus width control register (ABWCR) designates areas 0 to 7 all as 8-bit-access areas, the chip operates in 8-bit bus mode and port 4 is a generic input/output port.
Page 196 7.5.2 Register Descriptions Table 7.6 summarizes the registers of port 4. Table 7.6 Port 4 Registers Address* Name Abbreviation Initial Value H'EE003 Port 4 data direction register P4DDR H'00 H'FFFD3 Port 4 data register P4DR H'00 H'EE03E Port 4 input pull-up MOS control P4PCR H'00 register...
Page 197 ABWCR and P4DDR are not initialized in software standby mode. Therefore, if a transition is made to software standby mode while port 4 is functioning as an input/output port and a P4DDR bit is set to 1, the corresponding pin maintains its output state. Port 4 Data Register (P4DR): P4DR is an 8-bit readable/writable register that stores output data for port 4.
Page 198 Table 7.7 Input Pull-Up Transistor States (Port 4) Hardware Software Mode Reset Standby Mode Standby Mode Other Modes 1 to 5 8-bit bus mode On/off On/off 16-bit bus mode 6 and 7 On/off On/off Legend Off: The input pull-up transistor is always off. On/off: The input pull-up transistor is on if P4PCR = 1 and P4DDR = 0.
Page 199: Register Descriptions
7.6.2 Register Descriptions Table 7.8 summarizes the registers of port 5. Table 7.8 Port 5 Registers Initial Value Address* Name Abbreviation R/W Modes 1 to 4 Modes 5 to 7 H'EE004 Port 5 data direction register P5DDR H'FF H'F0 H'FFFD4 Port 5 data register P5DR H'F0 H'F0...
Page 200 In modes 5 to 7, P5DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P5DDR is initialized to H'FF in modes 1 to 4, and to H'F0 in modes 5 to 7, by a reset and in hardware standby mode.
Page 201: Port 4
P5PCR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Table 7.9 summarizes the states of the input pull-ups in each mode. Table 7.9 Input Pull-Up Transistor States (Port 5) Mode Reset Hardware Standby Mode...
Page 202 Modes 6 and 7 Port 6 pins Modes 1 to 5 (single-chip mode) (expanded modes) φ φ (input) / φ(output) P6 / (input)/ (output) P6 / (output) (input/output) P6 / (output) (input/output) Port 6 P6 / (output) (input/output) P6 / (output) (input/output) BACK...
Page 203 • Modes 1 to 5 (Expanded Modes) functions as the clock output pin (φ) or an input port. P6 is the clock output pin (ø) if the PSTOP bit in MSTRCH is cleared to 0 (initial value), and an input port if this bit is set to 1. function as bus control output pins (LWR, HWR, RD, and AS), regardless of the to P6 settings of bits P6...
Page 204 Table 7.11 Port 6 Pin Functions in Modes 1 to 5 Pin Functions and Selection Method /φ Bit PSTOP in MSTCRH selects the pin function. PSTOP φ output Pin function input Functions as LWR regardless of the setting of bit P6 LWR output Pin function Functions as HWR regardless of the setting of bit P6...
Page 205: Overview
Pin Functions and Selection Method /WAIT Bit WAITE in BCR and bit P6 DDR select the pin function as follows. WAITE WAIT input Pin function input output Note: * Do not set bit P6 DDR to 1. Port 7 7.8.1 Overview Port 7 is an 8-bit input port that is also used for analog input to the A/D converter and analog output from the D/A converter.
Page 206: Register Description
7.8.2 Register Description Table 7.12 summarizes the port 7 register. Port 7 is an input port, and port 7 has no data direction register. Table 7.12 Port 7 Data Register Address* Name Abbreviation Initial Value H'FFFD6 Port 7 data register P7DR Undetermined Note: * Lower 20 bits of the address in advanced mode.
Page 207: Port 8
Port 8 7.9.1 Overview Port 8 is a 5-bit input/output port that is also used for CS to CS output, IRQ to IRQ input, and A/D converter ADTRG input. Figure 7.8 shows the pin configuration of port 8. In modes 1 to 5 (expanded modes), port 8 can provide CS to CS output, IRQ to IRQ...
Page 208 7.9.2 Register Descriptions Table 7.13 summarizes the registers of port 8. Table 7.13 Port 8 Registers Initial Value Address* Name Abbreviation Mode 1 to 4 Mode 5 to 7 H'EE007 Port 8 data direction P8DDR H'F0 H'E0 register H'FFFD7 Port 8 data register P8DR H'E0 H'E0...
Page 209 P8DDR is initialized to H'F0 in modes 1 to 4, and to H'E0 in modes 5 to 7, by a reset and in hardware standby mode. In software standby mode P8DDR retains its previous setting. Therefore, if a transition is made to software standby mode while port 8 is functioning as an input/output port and a P8DDR bit is set to 1, the corresponding pin maintains its output state.
Page 210 Table 7.14 Port 8 Pin Functions in Modes 1 to 5 Pin Functions and Selection Method Bit P8 DDR selects the pin function as follows. Pin function input output /IRQ Bit P8 DDR selects the pin function as follows ADTRG Pin function input output...
Page 211 Table 7.15 Port 8 Pin Functions in Modes 6 and 7 Pin Functions and Selection Method Bit P8 DDR selects the pin function as follows. Pin function input output /IRQ /ADTRG Bit P8 DDR selects the pin function as follows. Pin function input output...
Page 212 7.10 Port 9 7.10.1 Overview Port 9 is a 6-bit input/output port that is also used for input and output (TxD , TxD , RxD , RxD ) by serial communication interface channels 0 and 1 (SCI0 and SCI1), and for IRQ , SCK and IRQ input.
Page 213: Register Descriptions
7.10.2 Register Descriptions Table 7.16 summarizes the registers of port 9. Table 7.16 Port 9 Registers Address* Name Abbreviation Initial Value H'EE008 Port 9 data direction register P9DDR H'C0 H'FFFD8 Port 9 data register P9DR H'C0 Note: * Lower 20 bits of the address in advanced mode. Port 9 Data Direction Register (P9DDR): P9DDR is an 8-bit write-only register that can select input or output for each pin in port 9.
Page 214 Port 9 Data Register (P9DR): P9DR is an 8-bit readable/writable register that stores output data for port 9. When port 9 functions as an output port, the value of this register is output. When a bit in P9DDR is set to 1, if port 9 is read the value of the corresponding P9DR bit is returned. When a bit in P9DDR is cleared to 0, if port 9 is read the corresponding pin logic level is read.
Page 215 Table 7.17 Port 9 Pin Functions Pin Functions and Selection Method /SCK /IRQ Bit C/A in SMR of SCI1, bits CKE0 and CKE1 in SCR, and bit P9 select the pin function as follows. CKE1 — CKE0 — — — —...
Page 216 Pin Functions and Selection Method /TxD Bit TE in SCR of SCI1, bit SMIF in SCMR, and bit P9 DDR select the pin function as follows. SMIF — — — Pin function input output output TxD output* Note: * Functions as the TxD output pin, but there are two states: one in which the pin is driven, and another in which the pin is at high- impedance.
Page 217: Overview
7.11 Port A 7.11.1 Overview Port A is an 8-bit input/output port that is also used for output (TP to TP ) from the programmable timing pattern controller (TPC), input and output (TIOCB , TIOCA , TIOCB , TIOCA , TIOCB TIOCA , TCLKD, TCLKC, TCLKB, TCLKA) by the 16-bit timer, clock input (TCLKD, TCLKC, TCLKB, TCLKA) to the 8-bit timer, and address output (A...
Page 218 Port A pins PA /TP /TIOCB /A PA /TP /TIOCA /A PA /TP /TIOCB /A PA /TP /TIOCA /A Port A PA /TP /TIOCB /TCLKD PA /TP /TIOCA /TCLKC PA /TP /TCLKB PA /TP /TCLKA Pin functions in modes 1, 2, 6 and 7 PA (input/output)/TP (output)/TIOCB (input/output) PA (input/output)/TP (output)/TIOCA (input/output) PA (input/output)/TP (output)/TIOCB (input/output)
Page 219: Register Descriptions
7.11.2 Register Descriptions Table 7.18 summarizes the registers of port A. Table 7.18 Port A Registers Initial Value Address* Name Modes 1, 2, 5, 6 and 7 Modes 3, 4 H'EE009 Port A data direction PADDR H'00 H'80 register H'FFFD9 Port A data register PADR H'00...
Page 220 mode while port A is functioning as an input/output port and a PADDR bit is set to 1, the corresponding pin maintains its output state. Port A Data Register (PADR): PADR is an 8-bit readable/writable register that stores output data for port A. When port A functions as an output port, the value of this register is output. When a bit in PADDR is set to 1, if port A is read the value of the corresponding PADR bit is returned.
Page 221 Table 7.19 Port A Pin Functions (Modes 1, 2, 6, and 7) Pin Functions and Selection Method Bit PWM2 in TMDR, bits IOB2 to IOB0 in TIOR2, bit NDER7 in NDERA, and bit TIOCB PA 7 DDR select the pin function as follows. 16-bit timer channel 2 settings (1) in table below...
Page 222 Pin Functions and Selection Method Bit PWM1 in TMDR, bits IOB2 to IOB0 in TIOR1, bit NDER5 in NDERA, and bit TIOCB DDR select the pin function as follows. 16-bit timer channel 1 settings (1) in table below (2) in table below —...
Page 223 Table 7.20 Port A Pin Functions (Modes 3 to 5) Pin Functions and Selection Method Modes 3 and 4: Always used as A output. TIOCB Pin function output Mode 5: Bit PWM2 in TMDR, bits IOB2 to IOB0 in TIOR2, bit NDER7 in NDERA, bit A20E in BRCR, and bit PA DDR select the pin function as follows.
Page 224 Pin Functions and Selection Method Bit PWM2 in TMDR, bits IOA2 to IOA0 in TIOR2, bit NDER6 in NDERA, bit A21E in TIOCA BRCR, and bit PA DDR select the pin function as follows. A21E 16-bit timer channel 2 settings (1) in table below (2) in table below —...
Page 225 Pin Functions and Selection Method Bit PWM1 in TMDR, bits IOA2 to IOA0 in TIOR1, bit NDER4 in NDERA, bit A23E in TIOCA BRCR, and bit PA DDR select the pin function as follows. A23E 16-bit timer channel 1 settings (1) in table below (2) in table below —...
Page 226 Table 7.21 Port A Pin Functions (Modes 1 to 7) Pin Functions and Selection Method Bit PWM0 in TMDR, bits IOB2 to IOB0 in TIOR0, bits TPSC2 to TPSC0 in 16TCR2 to TIOCB 16TCR0 of the 16-bit timer, bits CKS2 to CKS0 in 8TCR2 of the 8-bit timer, bit TCLKD NDER3 in NDERA, and bit PA DDR select the pin function as follows.
Page 227 Pin Functions and Selection Method Bit PWM0 in TMDR, bits IOA2 to IOA0 in TIOR0, bits TPSC2 to TPSC0 in 16TCR2 to TIOCA 16TCR0 of the 16-bit timer, bits CKS2 to CKS0 in 8TCR0 of the 8-bit timer, bit TCLKC NDER2 in NDERA, and bit PA DDR select the pin function as follows.
Page 228 Pin Functions and Selection Method Bit MDF in TMDR, bits TPSC2 to TPSC0 in 16TCR2 to 16TCR0 of the 16-bit timer, TCLKB bits CKS2 to CKS0 in 8TCR3 of the 8-bit timer, bit NDER1 in NDERA, and bit DDR select the pin function as follows. NDER1 —...
Page 229: Port B
7.12 Port B 7.12.1 Overview Port B is an 8-bit input/output port that is also used for output (TP to TP ) from the programmable timing pattern controller (TPC), input/output (TMIO , TMO , TMIO , TMO ) by the 8-bit timer, and CS to CS output.
Page 230 Port B pins Port B /TMIO /TMO /TP /TMIO /TP /TMO Pin functions in modes 1 to 5 (input/output)/TP (output) (input/output)/TP (output) (input/output)/TP (output) (input/output)/TP (output) (input/output)/TP (output) /TMIO (input/output) /CS (output) (input/output)/TP (output) /TMO (output) /CS (output) (input/output)/TP (output) /TMIO (input/output) /CS (output) (input/output)/TP...
Page 231: Register Descriptions
7.12.2 Register Descriptions Table 7.22 summarizes the registers of port B. Table 7.22 Port B Registers Address* Name Abbreviation Initial Value H'EE00A Port B data direction register PBDDR H'00 H'FFFDA Port B data register PBDR H'00 Note: * Lower 20 bits of the address in advanced mode. Port B Data Direction Register (PBDDR): PBDDR is an 8-bit write-only register that can select input or output for each pin in port B.
Page 232 Port B Data Register (PBDR): PBDR is an 8-bit readable/writable register that stores output data for pins port B. When port B functions as an output port, the value of this register is output. When a bit in PBDDR is set to 1, if port B is read the value of the corresponding PBDR bit is returned. When a bit in PBDDR is cleared to 0, if port B is read the corresponding pin logic level is read.
Page 233 Table 7.23 Port B Pin Functions (Modes 1 to 5) Pin Functions and Selection Method Bit NDER15 in NDERB and bit PB DDR select the pin function as follows. NDER15 — Pin function input output output Bit NDER14 in NDERB and bit PB DDR select the pin function as follows.
Page 234 Pin Functions and Selection Method Bits OIS3/2 and OS1/0 in 8TCSR2, bit CS5E in CSCR, bit NDER10 in NDERB, and bit PB DDR select the pin function as follows. OIS3/2 and All 0 Not all 0 OS1/0 CS5E — — —...
Page 235 Table 7.24 Port B Pin Functions (Modes 6 and 7) Pin Functions and Selection Method Bit NDER15 in NDERB and bit PB DDR select the pin function as follows. NDER15 — Pin function input output output Bit NDER14 in NDERB and bit PB DDR select the pin function as follows.
Page 236 Pin Functions and Selection Method Bits OIS3/2 and OS1/0 in 8TCSR2, bit NDER10 in NDERB, and bit PB DDR select the pin function as follows. OIS3/2 and All 0 Not all 0 OS1/0 — NDER10 — — Pin function input output output output...
Page 237: 16-Bit Timer
Section 8 16-Bit Timer Overview The H8/3062 Series has built-in 16-bit timer module with three 16-bit counter channels. 8.1.1 Features 16-bit timer features are listed below. • Capability to process up to 6 pulse outputs or 6 pulse inputs • Six general registers (GRs, two per channel) with independently-assignable output compare or input capture functions •...
Page 238 • Output triggering of programmable timing pattern controller (TPC) Compare match/input capture signals from channels 0 to 2 can be used as TPC output triggers. Table 8.1 summarizes the 16-bit timer functions. Table 8.1 16-bit timer Functions Item Channel 0 Channel 1 Channel 2 Internal clocks: φ, φ/2, φ/4, φ/8...
Page 239: Block Diagrams
8.1.2 Block Diagrams 16-bit timer Block Diagram (Overall): Figure 8.1 is a block diagram of the 16-bit timer. IMIA0 to IMIA2 TCLKA to TCLKD Clock selector IMIB0 to IMIB2 φ, φ/2, φ/4, φ/8 OVI0 to OVI2 Control logic TIOCA to TIOCA TIOCB to TIOCB TSTR...
Page 240 Block Diagram of Channels 0 and 1: 16-bit timer channels 0 and 1 are functionally identical. Both have the structure shown in figure 8.2. TCLKA to TCLKD TIOCA Clock selector TIOCB φ, φ/2, φ/4, φ/8 Control logic IMIA0 Comparator IMIB0 OVI0 Module data bus Legend:...
Page 241 Block Diagram of Channel 2: Figure 8.3 is a block diagram of channel 2 TCLKA to TCLKD TIOCA Clock selector TIOCB φ, φ/2, φ/4, φ/8 Control logic IMIA2 IMIB2 Comparator OVI2 Module data bus Legend: 16TCNT2: Timer counter 2 (16 bits) GRA2, GRB2: General registers A2 and B2 (input capture/output compare registers) (16 bits ×...
Page 242: Pin Configuration
8.1.3 Pin Configuration Table 8.2 summarizes the 16-bit timer pins. Table 8.2 16-bit timer Pins Abbre- Input/ Channel Name viation Output Function Common Clock input A TCLKA Input External clock A input pin (phase-A input pin in phase counting mode) Clock input B TCLKB Input...
Page 243: Register Configuration
8.1.4 Register Configuration Table 8.3 summarizes the 16-bit timer registers. Table 8.3 16-bit timer Registers Abbre- Initial Channel Address* Name viation Value Common H'FFF60 Timer start register TSTR H'F8 H'FFF61 Timer synchro register TSNC H'F8 H'FFF62 Timer mode register TMDR H'98 H'FFF63 Timer output level setting register...
Page 244: Register Descriptions
Abbre- Initial Channel Address* Name viation Value H'FFF78 Timer control register 2 16TCR2 H'80 H'FFF79 Timer I/O control register 2 TIOR2 H'88 H'FFF7A Timer counter 2H 16TCNT2H R/W H'00 H'FFF7B Timer counter 2L 16TCNT2L R/W H'00 H'FFF7C General register A2H GRA2H H'FF H'FFF7D...
Page 245: Timer Synchro Register (Tsnc)
Bit 1—Counter Start 1 (STR1): Starts and stops timer counter 1 (16TCNT1). Bit 1 STR1 Description 16TCNT1 is halted (Initial value) 16TCNT1 is counting Bit 0—Counter Start 0 (STR0): Starts and stops timer counter 0 (16TCNT0). Bit 0 STR0 Description 16TCNT0 is halted (Initial value) 16TCNT0 is counting...
Page 246: Timer Mode Register (Tmdr)
Bit 1—Timer Sync 1 (SYNC1): Selects whether channel 1 operates independently or synchronously. Bit 1 SYNC1 Description Channel 1’s timer counter (16TCNT1) operates independently (Initial value) 16TCNT1 is preset and cleared independently of other channels Channel 1 operates synchronously 16TCNT1 can be synchronously preset and cleared Bit 0—Timer Sync 0 (SYNC0): Selects whether channel 0 operates independently or synchronously.
Page 247 Bit 7—Reserved: This bit cannot be modified and is always read as 1. Bit 6—Phase Counting Mode Flag (MDF): Selects whether channel 2 operates normally or in phase counting mode. Bit 6 Description Channel 2 operates normally (Initial value) Channel 2 operates in phase counting mode When MDF is set to 1 to select phase counting mode, 16TCNT2 operates as an up/down-counter and pins TCLKA and TCLKB become counter clock input pins.
Page 248 Bit 2—PWM Mode 2 (PWM2): Selects whether channel 2 operates normally or in PWM mode. Bit 2 PWM2 Description Channel 2 operates normally (Initial value) Channel 2 operates in PWM mode When bit PWM2 is set to 1 to select PWM mode, pin TIOCA becomes a PWM output pin.
Page 249: Timer Interrupt Status Register A (Tisra)
8.2.4 Timer Interrupt Status Register A (TISRA) TISRA is an 8-bit readable/writable register that indicates GRA compare match or input capture and enables or disables GRA compare match and input capture interrupt requests. — IMIEA2 IMIEA1 IMIEA0 — IMFA2 IMFA1 IMFA0 Initial value Read/Write...
Page 250 Bit 5 IMIEA1 Description IMIA1 interrupt requested by IMFA1 flag is disabled (Initial value) IMIA1 interrupt requested by IMFA1 flag is enabled Bit 4—Input Capture/Compare Match Interrupt Enable A0 (IMIEA0): Enables or disables the interrupt requested by the IMFA0 flag when IMFA0 is set to 1. Bit 4 IMIEA0 Description...
Page 251: Timer Interrupt Status Register B (Tisrb)
Bit 0—Input Capture/Compare Match Flag A0 (IMFA0): This status flag indicates GRA0 compare match or input capture events. Bit 0 IMFA0 Description [Clearing condition] (Initial value) Read IMFA0 flag when IMFA0 =1, then write 0 in IMFA0 flag [Setting conditions] •...
Page 252 Bit 7—Reserved: This bit cannot be modified and is always read as 1. Bit 6—Input Capture/Compare Match Interrupt Enable B2 (IMIEB2): Enables or disables the interrupt requested by the IMFB2 when IMFB2 flag is set to 1. Bit 6 IMIEB2 Description IMIB2 interrupt requested by IMFB2 flag is disabled (Initial value)
Page 253 Bit 1—Input Capture/Compare Match Flag B1 (IMFB1): This status flag indicates GRB1 compare match or input capture events. Bit 1 IMFB1 Description [Clearing condition] (Initial value) Read IMFB1 flag when IMFB1 =1, then write 0 in IMFB1 flag [Setting conditions] •...
Page 254: Timer Interrupt Status Register C (Tisrc)
8.2.6 Timer Interrupt Status Register C (TISRC) TISRC is an 8-bit readable/writable register that indicates 16TCNT overflow or underflow and enables or disables overflow interrupt requests. — OVIE2 OVIE1 OVIE0 — OVF2 OVF1 OVF0 Initial value Read/Write — — R/(W)* R/(W)* R/(W)* Overflow flags 2 to 0...
Page 255 Bit 4—Overflow Interrupt Enable 0 (OVIE0): Enables or disables the interrupt requested by the OVF0 when OVF0 flag is set to 1. Bit 4 OVIE0 Description OVI0 interrupt requested by OVF0 flag is disabled (Initial value) OVI0 interrupt requested by OVF0 flag is enabled Bit 3—Reserved: This bit cannot be modified and is always read as 1.
Page 256: Timer Counters (16Tcnt)
8.2.7 Timer Counters (16TCNT) 16TCNT is a 16-bit counter. The 16-bit timer has three 16TCNTs, one for each channel. Channel Abbreviation Function 16TCNT0 Up-counter 16TCNT1 16TCNT2 Phase counting mode: up/down-counter Other modes: up-counter Initial value Read/Write Each 16TCNT is a 16-bit readable/writable register that counts pulse inputs from a clock source. The clock source is selected by bits TPSC2 to TPSC0 in 16TCR.
Page 257: General Registers (Gra, Grb)
8.2.8 General Registers (GRA, GRB) The general registers are 16-bit registers. The 16-bit timer has 6 general registers, two in each channel. Channel Abbreviation Function GRA0, GRB0 Output compare/input capture register GRA1, GRB1 GRA2, GRB2 Initial value Read/Write A general register is a 16-bit readable/writable register that can function as either an output compare register or an input capture register.
Page 258: Timer Control Registers (16Tcr)
8.2.9 Timer Control Registers (16TCR) 16TCR is an 8-bit register. The 16-bit timer has three 16TCRs, one in each channel. Channel Abbreviation Function 16TCR0 16TCR controls the timer counter. The 16TCRs in all channels are functionally identical. When phase counting 16TCR1 mode is selected in channel 2, the settings of bits CKEG1 and CKEG0 and TPSC2 to TPSC0 in 16TCR2 are ignored.
Page 259 Bits 6 and 5—Counter Clear 1 and 0 (CCLR1, CCLR0): These bits select how 16TCNT is cleared. Bit 6 Bit 5 CCLR1 CCLR0 Description 16TCNT is not cleared (Initial value) 16TCNT is cleared by GRA compare match or input capture* 16TCNT is cleared by GRB compare match or input capture* Synchronous clear: 16TCNT is cleared in synchronization with other synchronized timers*...
Page 260: Timer I/O Control Register (Tior)
When bit TPSC2 is cleared to 0 an internal clock source is selected, and the timer counts only falling edges. When bit TPSC2 is set to 1 an external clock source is selected, and the timer counts the edges selected by bits CKEG1 and CKEG0. When channel 2 is set to phase counting mode (MDF = 1 in TMDR), the settings of bits TPSC2 to TPSC0 in 16TCR2 are ignored.
Page 261 Bits 6 to 4—I/O Control B2 to B0 (IOB2 to IOB0): These bits select the GRB function. Bit 6 Bit 5 Bit 4 IOB2 IOB1 IOB0 Function GRB is an output No output at compare match (Initial value) compare register 0 output at GRB compare match* 1 output at GRB compare match* Output toggles at GRB compare match...
Page 262: Timer Output Level Setting Register C (Tolr)
8.2.11 Timer Output Level Setting Register C (TOLR) TOLR is an 8-bit write-only register that selects the timer output level for channels 0 to 2. — — TOB2 TOA2 TOB1 TOA1 TOB0 TOA0 Initial value Read/Write — — Output level setting A2 to A0, B2 to B0 These bits set the levels of the timer outputs (TIOCA to TIOCA...
Page 263 Bit 3—Output Level Setting B1 (TOB1): Sets the value of timer output TIOCB Bit 3 TOB1 Description TIOCB is 0 (Initial value) TIOCB is 1 Bit 2—Output Level Setting A1 (TOA1): Sets the value of timer output TIOCA Bit 2 TOA1 Description TIOCA...
Page 264: Cpu Interface
CPU Interface 8.3.1 16-Bit Accessible Registers The timer counters (16TCNTs), general registers A and B (GRAs and GRBs) are 16-bit registers, and are linked to the CPU by an internal 16-bit data bus. These registers can be written or read a word at a time, or a byte at a time.
Page 265 On-chip data bus Module Bus interface data bus 16TCNTH 16TCNTL Figure 8.6 Access to Timer Counter H (CPU Writes to 16TCNTH, Upper Byte) On-chip data bus Module Bus interface data bus 16TCNTH 16TCNTL Figure 8.7 Access to Timer Counter L (CPU Writes to 16TCNTL, Lower Byte) On-chip data bus Module Bus interface...
Page 266: 8-Bit Accessible Registers
On-chip data bus Module Bus interface data bus 16TCNTH 16TCNTL Figure 8.9 Access to Timer Counter L (CPU Reads 16TCNTL, Lower Byte) 8.3.2 8-Bit Accessible Registers The registers other than the timer counters and general registers are 8-bit registers. These registers are linked to the CPU by an internal 8-bit data bus.
Page 267: Operation
Operation 8.4.1 Overview A summary of operations in the various modes is given below. Normal Operation: Each channel has a timer counter and general registers. The timer counter counts up, and can operate as a free-running counter, periodic counter, or external event counter. GRA and GRB can be used for input capture or output compare.
Page 268 Counter setup Select counter clock Count operation Free-running counting Periodic counting Select counter clear source Select output compare register function Set period Start counter Start counter Periodic counter Free-running counter Figure 8.12 Counter Setup Procedure (Example) 1. Set bits TPSC2 to TPSC0 in 16TCR to select the counter clock source. If an external clock source is selected, set bits CKEG1 and CKEG0 in 16TCR to select the desired edge(s) of the external clock signal.
Page 269 • Free-running and periodic counter operation A reset leaves the counters (16TCNTs) in 16-bit timer channels 0 to 2 all set as free-running counters. A free-running counter starts counting up when the corresponding bit in TSTR is set to 1. When the count overflows from H'FFFF to H'0000, the OVF flag is set to 1 in TISRC. After the overflow, the counter continues counting up from H'0000.
Page 270 • 16TCNT count timing  Internal clock source Bits TPSC2 to TPSC0 in 16TCR select the system clock (φ) or one of three internal clock sources obtained by prescaling the system clock (φ/2, φ/4, φ/8). Figure 8.15 shows the timing. φ...
Page 271 Waveform Output by Compare Match: In 16-bit timer channels 0, 1 compare match A or B can cause the output at the TIOCA or TIOCB pin to go to 0, go to 1, or toggle. In channel 2 the output can only go to 0 or go to 1.
Page 272 • Examples of waveform output Figure 8.18 shows examples of 0 and 1 output. 16TCNT operates as a free-running counter, 0 output is selected for compare match A, and 1 output is selected for compare match B. When the pin is already at the selected output level, the pin level does not change. 16TCNT value H'FFFF H'0000...
Page 273 • Output compare output timing The compare match signal is generated in the last state in which 16TCNT and the general register match (when 16TCNT changes from the matching value to the next value). When the compare match signal is generated, the output value selected in TIOR is output at the output compare pin (TIOCA or TIOCB).
Page 274 • Sample setup procedure for input capture Figure 8.21 shows a sample procedure for setting up input capture. Input selection Set TIOR to select the input capture function of a general register and the rising edge, falling edge, or both edges of the input capture signal. Clear the DDR bit to 0 before making these TIOR settings.
Page 275: Synchronization
• Input capture signal timing Input capture on the rising edge, falling edge, or both edges can be selected by settings in TIOR. Figure 8.23 shows the timing when the rising edge is selected. The pulse width of the input capture signal must be at least 1.5 system clocks for single-edge capture, and 2.5 system clocks for capture of both edges.
Page 276 Setup for synchronization Select synchronization Synchronous preset Synchronous clear Clearing synchronized to this channel? Write to 16TCNT Select counter clear source Select counter clear source Start counter Start counter Synchronous preset Counter clear Synchronous clear Set the SYNC bits to 1 in TSNC for the channels to be synchronized. When a value is written in 16TCNT in one of the synchronized channels, the same value is simultaneously written in 16TCNT in the other channels.
Page 277: Pwm Mode
Value of 16TCNT0 to 16TCNT2 Cleared by compare match with GRB0 GRB0 GRB1 GRA0 GRB2 GRA1 GRA2 H'0000 TIOCA TIOCA TIOCA Figure 8.25 Synchronization (Example) 8.4.4 PWM Mode In PWM mode GRA and GRB are paired and a PWM waveform is output from the TIOCA pin. GRA specifies the time at which the PWM output changes to 1.
Page 278 Sample Setup Procedure for PWM Mode: Figure 8.26 shows a sample procedure for setting up PWM mode. PWM mode Set bits TPSC2 to TPSC0 in 16TCR to select the counter clock source. If an external clock source is selected, set bits CKEG1 and CKEG0 in 16TCR to Select counter clock select the desired edge(s) of the...
Page 279 Examples of PWM Mode: Figure 8.27 shows examples of operation in PWM mode. In PWM mode TIOCA becomes an output pin. The output goes to 1 at compare match with GRA, and to 0 at compare match with GRB. In the examples shown, 16TCNT is cleared by compare match with GRA or GRB. Synchronized operation and free-running counting are also possible.
Page 280 Figure 8.28 shows examples of the output of PWM waveforms with duty cycles of 0% and 100%. If the counter is cleared by compare match with GRB, and GRA is set to a higher value than GRB, the duty cycle is 0%. If the counter is cleared by compare match with GRA, and GRB is set to a higher value than GRA, the duty cycle is 100%.
Page 281: Phase Counting Mode
8.4.5 Phase Counting Mode In phase counting mode the phase difference between two external clock inputs (at the TCLKA and TCLKB pins) is detected, and 16TCNT2 counts up or down accordingly. In phase counting mode, the TCLKA and TCLKB pins automatically function as external clock input pins and 16TCNT2 becomes an up/down-counter, regardless of the settings of bits TPSC2 to TPSC0, CKEG1, and CKEG0 in 16TCR2.
Page 282 Example of Phase Counting Mode: Figure 8.30 shows an example of operations in phase counting mode. Table 8.5 lists the up-counting and down-counting conditions for 16TCNT2. In phase counting mode both the rising and falling edges of TCLKA and TCLKB are counted. The phase difference between TCLKA and TCLKB must be at least 1.5 states, the phase overlap must also be at least 1.5 states, and the pulse width must be at least 2.5 states.
Page 283: 16-Bit Timer Output Timing
8.4.6 16-Bit Timer Output Timing The initial value of 16-bit timer output when a timer count operation begins can be specified arbitrarily by making a setting in TOLR. Figure 8.32 shows the timing for setting the initial value with TOLR. Only write to TOLR when the corresponding bit in TSTR is cleared to 0.
Page 284: Interrupts
Interrupts The 16-bit timer has two types of interrupts: input capture/compare match interrupts, and overflow interrupts. 8.5.1 Setting of Status Flags Timing of Setting of IMFA and IMFB at Compare Match: IMFA and IMFB are set to 1 by a compare match signal generated when 16TCNT matches a general register (GR).
Page 285 Timing of Setting of IMFA and IMFB by Input Capture: IMFA and IMFB are set to 1 by an input capture signal. The 16TCNT contents are simultaneously transferred to the corresponding general register. Figure 8.34 shows the timing. φ Input capture signal 16TCNT Figure 8.34 Timing of Setting of IMFA and IMFB by Input Capture...
Page 286: Timing Of Clearing Of Status Flags
Timing of Setting of Overflow Flag (OVF): OVF is set to 1 when 16TCNT overflows from H'FFFF to H'0000 or underflows from H'0000 to H'FFFF. Figure 8.35 shows the timing. φ 16TCNT Overflow signal Figure 8.35 Timing of Setting of OVF 8.5.2 Timing of Clearing of Status Flags If the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is...
Page 287 8.5.3 Interrupt Sources Each 16-bit timer channel can generate a compare match/input capture A interrupt, a compare match/input capture B interrupt, and an overflow interrupt. In total there are nine interrupt sources of three kinds, all independently vectored. An interrupt is requested when the interrupt request flag are set to 1.
Page 288: Usage Notes
Usage Notes This section describes contention and other matters requiring special attention during 16-bit timer operations. Contention between 16TCNT Write and Clear: If a counter clear signal occurs in the T state of a 16TCNT write cycle, clearing of the counter takes priority and the write is not performed. See figure 8.37.
Page 289 Contention between 16TCNT Word Write and Increment: If an increment pulse occurs in the state of a 16TCNT word write cycle, writing takes priority and 16TCNT is not incremented. Figure 8.38 shows the timing in this case. 16TCNT word write cycle φ...
Page 290 Contention between 16TCNT Byte Write and Increment: If an increment pulse occurs in the or T state of a 16TCNT byte write cycle, writing takes priority and 16TCNT is not incremented. The byte data for which a write was not performed is not incremented, and retains its pre-write value.
Page 291 Contention between General Register Write and Compare Match: If a compare match occurs in the T state of a general register write cycle, writing takes priority and the compare match signal is inhibited. See figure 8.40. General register write cycle φ...
Page 292 Contention between 16TCNT Write and Overflow or Underflow: If an overflow occurs in the state of a 16TCNT write cycle, writing takes priority and the counter is not incremented. OVF set to 1.The same holds for underflow. See figure 8.41. 16TCNT write cycle φ...
Page 293 Contention between General Register Read and Input Capture: If an input capture signal occurs during the T state of a general register read cycle, the value before input capture is read. See figure 8.42. General register read cycle φ Address bus GR address Internal read signal Input capture signal...
Page 294 Contention between Counter Clearing by Input Capture and Counter Increment: If an input capture signal and counter increment signal occur simultaneously, the counter is cleared according to the input capture signal. The counter is not incremented by the increment signal. The value before the counter is cleared is transferred to the general register.
Page 295 Contention between General Register Write and Input Capture: If an input capture signal occurs in the T state of a general register write cycle, input capture takes priority and the write to the general register is not performed. See figure 8.44. General register write cycle φ...
Page 296 Note on Waveform Period Setting: When a counter is cleared by compare match, the counter is cleared in the last state at which the 16TCNT value matches the general register value, at the time when this value would normally be updated to the next count. The actual counter frequency is therefore given by the following formula: φ...
Page 297 16-bit timer Operating Modes Table 8.7 (a) 16-bit timer Operating Modes (Channel 0) Register Settings TSNC TMDR TIOR0 16TCR0 Synchro- Clear Clock Operating Mode nization FDIR PWM Select Select Synchronous preset SYNC0 = 1 — — PWM mode — — PWM0 = 1 —...
Page 298 Table 8.7 (b) 16-bit timer Operating Modes (Channel 1) Register Settings TSNC TMDR TIOR1 16TCR1 Synchro- Clear Clock Operating Mode nization FDIR PWM Select Select Synchronous preset SYNC1 = 1 — — PWM mode — — PWM1 = 1 — Output compare A —...
Page 299 Table 8.7 (c) 16-bit timer Operating Modes (Channel 2) Register Settings TSNC TMDR TIOR2 16TCR2 Synchro- Clear Clock Operating Mode nization FDIR PWM Select Select Synchronous preset SYNC2 = 1 — PWM mode — PWM2 = 1 — Output compare A —...
Page 300: 8-Bit Timers
Section 9 8-Bit Timers Overview The H8/3062 Series has a built-in 8-bit timer module with four channels (TMR0, TMR1, TMR2, and TMR3), based on 8-bit counters. Each channel has an 8-bit timer counter (8TCNT) and two 8-bit time constant registers (TCORA and TCORB) that are constantly compared with the 8TCNT value to detect compare match events.
Page 301 • Twelve interrupt sources There are twelve interrupt sources: four compare match sources, four compare match/input capture sources, four overflow sources. Two of the compare match sources and two of the combined compare match/input capture sources each have an independent interrupt vector. The remaining compare match interrupts, combined compare match/input capture interrupts, and overflow interrupts have one interrupt vector for two sources.
Page 302: Block Diagram
9.1.2 Block Diagram The 8-bit timers are divided into two groups of two channels each: group 0 comprising channels 0 and 1, and group 1 comprising channels 2 and 3. Figure 9.1 shows a block diagram of 8-bit timer group 0. External clock Internal clock sources...
Page 303: Pin Configuration
9.1.3 Pin Configuration Table 9.1 summarizes the input/output pins of the 8-bit timer module. Table 9.1 8-Bit Timer Pins Group Channel Name Abbreviation I/O Function Timer output Output Compare match output Timer clock input TCLKC Input Counter external clock input Timer input/output TMIO Compare match output/input capture input...
Page 304: Register Configuration
9.1.4 Register Configuration Table 9.2 summarizes the registers of the 8-bit timer module. Table 9.2 8-Bit Timer Registers Channel Address*1 Name Abbreviation R/W Initial value H'FFF80 Timer control register 0 8TCR0 H'00 H'FFF82 Timer control/status register 0 8TCSR0 R/(W)* H'00 H'FFF84 Time constant register A0 TCORA0...
Page 305: Register Descriptions
Register Descriptions 9.2.1 Timer Counters (8TCNT) 8TCNT0 8TCNT1 Initial value Read/Write 8TCNT2 8TCNT3 Initial value Read/Write The timer counters (8TCNT) are 8-bit readable/writable up-counters that increment on pulses generated from an internal or external clock source. The clock source is selected by clock select bits 2 to 0 (CKS2 to CKS0) in the timer control register (8TCR).
Page 306: Time Constant Registers A (Tcora)
9.2.2 Time Constant Registers A (TCORA) TCORA0 to TCORA3 are 8-bit readable/writable registers. TCORA0 TCORA1 Initial value Read/Write TCORA2 TCORA3 Initial value Read/Write The TCORA0 and TCORA1 pair, and the TCORA2 and TCORA3 pair, can each be accessed as a 16-bit register by word access.
Page 307: Time Constant Registers B (Tcorb)
9.2.3 Time Constant Registers B (TCORB) TCORB0 TCORB1 Initial value Read/Write TCORB2 TCORB3 Initial value Read/Write TCORB0 to TCORB3 are 8-bit readable/writable registers. The TCORB0 and TCORB1 pair, and the TCORB2 and TCORB3 pair, can each be accessed as a 16-bit register by word access. The TCORB value is constantly compared with the 8TCNT value.
Page 308: Timer Control Register (8Tcr)
9.2.4 Timer Control Register (8TCR) CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Initial value Read/Write 8TCR is an 8-bit readable/writable register that selects the 8TCNT input clock, gives the 8TCNT clearing specification, and enables interrupt requests. 8TCR is initialized to H'00 by a reset and in standby mode. For the timing, see section 9.4, Operation.
Page 309 Bits 4 and 3—Counter Clear 1 and 0 (CCLR1, CCLR0): These bits specify the 8TCNT clearing source. Compare match A or B, or input capture B, can be selected as the clearing source. Bit 4 Bit 3 CCLR1 CCLR0 Description Clearing is disabled (Initial value) Cleared by compare match A...
Page 310 Bit 2 Bit 1 Bit 0 CSK2 CSK1 CSK0 Description Clock input disabled (Initial value) Internal clock, counted on falling edge of φ/8 Internal clock, counted on falling edge of φ/64 Internal clock, counted on falling edge of φ/8192 Channel 0 (16-bit count mode): Count on 8TCNT1 overflow signal* Channel 1 (compare match count mode): Count on 8TCNT0 compare match A*...
Page 311: Timer Control/Status Registers (8Tcsr)
9.2.5 Timer Control/Status Registers (8TCSR) 8TCSR0 CMFB CMFA OIS3 OIS2 ADTE Initial value Read/Write R/(W)* R/(W)* R/(W)* 8TCSR2 CMFB CMFA — OIS3 OIS2 Initial value Read/Write R/(W)* R/(W)* R/(W)* — 8TCSR1, 8TCSR3 CMFB CMFA OIS3 OIS2 Initial value Read/Write R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
Page 312 Bit 7—Compare Match/Input Capture Flag B (CMFB): Status flag that indicates the occurrence of a TCORB compare match or input capture. Bit 7 CMFB Description [Clearing condition] (Initial value) Read CMFB when CMFB = 1, then write 0 in CMFB [Setting conditions] •...
Page 313 Bit 4—A/D Trigger Enable (ADTE) (In 8TCSR0): In combination with TRGE in the A/D control register (ADCR), enables or disables A/D converter start requests by compare match A or an external trigger. Bit 4 TRGE* ADTE Description A/D converter start requests by compare match A or external trigger pin (ADTRG) input are disabled (Initial value) A/D converter start requests by compare match A or external trigger pin...
Page 314 Table 9.3 Operation of Channels 0 and 1 when Bit ICE is Set to 1 in 8TCSR1 Register Register Timer Output Register Function Status Flag Change Capture Input Interrupt Request TCORA0 Compare match CMFA changed from 0 output CMIA0 interrupt request operation to 1 in 8TCSR0 by controllable...
Page 315 Bits 3 and 2—Output/Input Capture Edge Select B3 and B2 (OIS3, OIS2): In combination with the ICE bit in 8TCSR1 (8TCSR3), these bits select the compare match B output level or the input capture input detected edge. The function of TCORB1 (TCORB3) depends on the setting of bit 4 of 8TCSR1 (8TCSR3). ICE Bit in 8TCSR1 Bit 3...
Page 316: Cpu Interface
CPU Interface 9.3.1 8-Bit Registers 8TCNT, TCORA, TCORB, 8TCR, and 8TCSR are 8-bit registers. These registers are connected to the CPU by an internal 16-bit data bus and can be read and written a word at a time or a byte at a time.
Page 317 Internal data bus Module data bus interface 8TCNTH0 8TCNTL1 Figure 9.5 8TCNT1 Access Operation (CPU Writes to 8TCNT1, Lower Byte) Internal data bus Module data bus interface 8TCNT0 8TCNT1 Figure 9.6 8TCNT0 Access Operation (CPU Reads 8TCNT0, Upper Byte) Internal data bus Module data bus interface 8TCNT0 8TCNT1...
Page 318: Operation
Operation 9.4.1 8TCNT Count Timing 8TCNT is incremented by input clock pulses (either internal or external). Internal Clock: Three different internal clock signals (φ/8, φ/64, or φ/8192) divided from the system clock (φ) can be selected, by setting bits CKS2 to CKS0 in 8TCR. Figure 9.8 shows the count timing.
Page 319: Compare Match Timing
φ External clock input 8TCNT input clock N–1 8TCNT Figure 9.9 Count Timing for External Clock Input (Both-Edge Detection) 9.4.2 Compare Match Timing Timer Output Timing: When compare match A or B occurs, the timer output is as specified by the OIS3, OIS2, OS1, and OS0 bits in 8TCSR (unchanged, 0 output, 1 output, or toggle output).
Page 320: Input Capture Signal Timing
Clear by Compare Match: Depending on the setting of the CCLR1 and CCLR0 bits in 8TCR, 8TCNT can be cleared when compare match A or B occurs, Figure 9.11 shows the timing of this operation. φ Compare match signal 8TCNT H'00 Figure 9.11 Timing of Clear by Compare Match Clear by Input Capture: Depending on the setting of the CCLR1 and CCLR0 bits in 8TCR,...
Page 321: Timing Of Status Flag Setting
φ Input capture input Input capture signal 8TCNT TCORB Figure 9.13 Timing of Input Capture Input Signal 9.4.4 Timing of Status Flag Setting Timing of CMFA/CMFB Flag Setting when Compare Match Occurs: The CMFA and CMFB flags in 8TCSR are set to 1 by the compare match signal output when the TCORA or TCORB and 8TCNT values match.
Page 322: Operation With Cascaded Connection
φ 8TCNT TCORB Input capture signal CMFB Figure 9.15 CMFB Flag Setting Timing when Input Capture Occurs Timing of Overflow Flag (OVF) Setting: The OVF flag in 8TCSR is set to 1 by the overflow signal generated when 8TCNT overflows (from H'FF to H'00). Figure 9.16 shows the timing in this case.
Page 323 16-Bit Count Mode • Channels 0 and 1: When bits CKS2 to CKS0 are set to (100) in 8TCR0, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. ...
Page 324  Setting when Input Capture Occurs • The CMFB flag is set to 1 in 8TCSR2 and 8TCSR3 when the ICE bit is 1 in TCSR3 and input capture occurs. • TMIO pin input capture input signal edge detection is selected by bits OIS3 and OIS2 in 8TCSR2.
Page 325: Input Capture Setting
9.4.6 Input Capture Setting The 8TCNT value can be transferred to TCORB on detection of an input edge on the input capture/output compare pin (TMIO or TMIO ). Rising edge, falling edge, or both edge detection can be selected. In 16-bit count mode, 16-bit input capture can be used. Setting Input Capture Operation in 8-Bit Timer Mode (Normal Operation) •...
Page 326: Interrupt
Interrupt 9.5.1 Interrupt Sources The 8-bit timer unit can generate three types of interrupt: compare match A and B (CMIA and CMIB) and overflow (TOVI). Table 9.5 shows the interrupt sources and their priority order. Each interrupt source is enabled or disabled by the corresponding interrupt enable bit in 8TCR. A separate interrupt request signal is sent to the interrupt controller by each interrupt source.
Page 327: A/D Converter Activation
9.5.2 A/D Converter Activation The A/D converter can only be activated by channel 0 compare match A. If the ADTE bit setting is 1 when the CMFA flag in 8TCSR0 is set to 1 by generation of channel 0 compare match A, an A/D conversion start request will be issued to the A/D converter. If the TRGE bit in ADCR is 1 at this time, the A/D converter will be started.
Page 328: Usage Notes
Usage Notes Note that the following kinds of contention can occur in 8-bit timer operation. 9.7.1 Contention between 8TCNT Write and Clear If a timer counter clear signal occurs in the T state of a 8TCNT write cycle, clearing of the counter takes priority and the write is not performed.
Page 329: Contention Between 8Tcnt Write And Increment
9.7.2 Contention between 8TCNT Write and Increment If an increment pulse occurs in the T state of a 8TCNT write cycle, writing takes priority and 8TCNT is not incremented. Figure 9.19 shows the timing in this case. 8TCNT write cycle φ...
Page 330: Contention Between Tcor Write And Compare Match
9.7.3 Contention between TCOR Write and Compare Match If a compare match occurs in the T state of a TCOR write cycle, writing takes priority and the compare match signal is inhibited. Figure 9.20 shows the timing in this case. TCOR write cycle φ...
Page 331: Contention Between Tcor Read And Input Capture
9.7.4 Contention between TCOR Read and Input Capture If an input capture signal occurs in the T state of a TCOR read cycle, the value before input capture is read. Figure 9.21 shows the timing in this case. TCORB read cycle φ...
Page 332: Contention Between Counter Clearing By Input Capture And Counter Increment
9.7.5 Contention between Counter Clearing by Input Capture and Counter Increment If an input capture signal and counter increment signal occur simultaneously, counter clearing by the input capture signal takes priority and the counter is not incremented. The value before the counter is cleared is transferred to TCORB.
Page 333: Contention Between Tcor Write And Input Capture
9.7.6 Contention between TCOR Write and Input Capture If an input capture signal occurs in the T state of a TCOR write cycle, input capture takes priority and the write to TCOR is not performed. Figure 9.23 shows the timing in this case. TCOR write cycle φ...
Page 334: Contention Between 8Tcnt Byte Write And Increment In 16-Bit Count Mode (Cascaded Connection)
9.7.7 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode (Cascaded Connection) If an increment pulse occurs in the T state of an 8TCNT byte write cycle in 16-bit count mode, the counter write takes priority and the byte data for which the write was performed is not incremented.
Page 335: Contention Between Compare Matches A And B
9.7.8 Contention between Compare Matches A and B If compare matches A and B occur at the same time, the 8-bit timer operates according to the relative priority of the output states set for compare match A and compare match B, as shown in Table 9.7.
Page 336 Table 9.8 Internal Clock Switchover and 8TCNT Operation CKS1 and CKS0 Write Timing 8TCNT Operation High → high switchover* Old clock source New clock source 8TCNT clock 8TCNT CKS bits rewritten High → low switchover* Old clock source New clock source 8TCNT clock 8TCNT...
Page 337 CKS1 and CKS0 Write Timing 8TCNT Operation Low → low switchover* Old clock source New clock source 8TCNT clock 8TCNT CKS bits rewritten Notes: 1. Including switchovers from the high level to the halted state, and from the halted state to the high level.
Page 338: Section 10 Programmable Timing Pattern Controller (Tpc)
10.1 Overview The H8/3062 Series has a built-in programmable timing pattern controller (TPC) that provides pulse outputs by using the 16-bit timer as a time base. The TPC pulse outputs are divided into 4- bit groups (group 3 to group 0) that can operate simultaneously and independently.
Page 339: Block Diagram
10.1.2 Block Diagram Figure 10.1 shows a block diagram of the TPC. 16-bit timer compare match signals PADDR PBDDR NDERA NDERB Control logic TPMR TPCR Internal data bus Pulse output pins, group 3 PBDR NDRB Pulse output pins, group 2 Pulse output pins, group 1 PADR...
Page 340: Pin Configuration
10.1.3 Pin Configuration Table 10.1 summarizes the TPC output pins. Table 10.1 TPC Pins Name Symbol Function TPC output 0 Output Group 0 pulse output TPC output 1 Output TPC output 2 Output TPC output 3 Output TPC output 4 Output Group 1 pulse output TPC output 5...
Page 341: Register Configuration
10.1.4 Register Configuration Table 10.2 summarizes the TPC registers. Table 10.2 TPC Registers Address* Name Abbreviation Initial Value H'EE009 Port A data direction register PADDR H'00 H'FFFD9 Port A data register PADR R/(W)* H'00 H'EE00A Port B data direction register PBDDR H'00 H'FFFDA...
Page 342: Register Descriptions
10.2 Register Descriptions 10.2.1 Port A Data Direction Register (PADDR) PADDR is an 8-bit write-only register that selects input or output for each pin in port A. PA DDR PA DDR PA DDR PA DDR PA DDR PA DDR PA DDR PA DDR Initial value Read/Write...
Page 343: Port B Data Direction Register (Pbddr)
10.2.3 Port B Data Direction Register (PBDDR) PBDDR is an 8-bit write-only register that selects input or output for each pin in port B. PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR Initial value Read/Write Port B data direction 7 to 0...
Page 344: Next Data Register A (Ndra)
10.2.5 Next Data Register A (NDRA) NDRA is an 8-bit readable/writable register that stores the next output data for TPC output groups 1 and 0 (pins TP to TP ). During TPC output, when an 16-bit timer compare match event specified in TPCR occurs, NDRA contents are transferred to the corresponding bits in PADR.
Page 345 Different Triggers for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered by different compare match events, the address of the upper 4 bits of NDRA (group 1) is H'FFFA5 and the address of the lower 4 bits (group 0) is H'FFFA7. Bits 3 to 0 of address H'FFFA5 and bits 7 to 4 of address H'FFFA7 are reserved bits that cannot be modified and always read 1.
Page 346: Next Data Register B (Ndrb)
10.2.6 Next Data Register B (NDRB) NDRB is an 8-bit readable/writable register that stores the next output data for TPC output groups 3 and 2 (pins TP to TP ). During TPC output, when an 16-bit timer compare match event specified in TPCR occurs, NDRB contents are transferred to the corresponding bits in PBDR.
Page 347 Different Triggers for TPC Output Groups 2 and 3: If TPC output groups 2 and 3 are triggered by different compare match events, the address of the upper 4 bits of NDRB (group 3) is H'FFFA4 and the address of the lower 4 bits (group 2) is H'FFFA6. Bits 3 to 0 of address H'FFFA4 and bits 7 to 4 of address H'FFFA6 are reserved bits that cannot be modified and always read 1.
Page 348: Next Data Enable Register A (Ndera)
10.2.7 Next Data Enable Register A (NDERA) NDERA is an 8-bit readable/writable register that enables or disables TPC output groups 1 and 0 to TP ) on a bit-by-bit basis. NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 Initial value Read/Write Next data enable 7 to 0 These bits enable or disable...
Page 349: Next Data Enable Register B (Nderb)
10.2.8 Next Data Enable Register B (NDERB) NDERB is an 8-bit readable/writable register that enables or disables TPC output groups 3 and 2 to TP ) on a bit-by-bit basis. NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial value Read/Write Next data enable 15 to 8 These bits enable or disable...
Page 350: Tpc Output Control Register (Tpcr)
10.2.9 TPC Output Control Register (TPCR) TPCR is an 8-bit readable/writable register that selects output trigger signals for TPC outputs on a group-by-group basis. G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value Read/Write Group 3 compare match select 1 and 0 These bits select the compare match Group 2 compare...
Page 351 Bits 5 and 4—Group 2 Compare Match Select 1 and 0 (G2CMS1, G2CMS0): These bits select the compare match event that triggers TPC output group 2 (TP to TP Bit 5 Bit 4 G2CMS1 G2CMS0 Description TPC output group 2 (TP to TP ) is triggered by compare match in 16-bit timer channel 0...
Page 352: Tpc Output Mode Register (Tpmr)
10.2.10 TPC Output Mode Register (TPMR) TPMR is an 8-bit readable/writable register that selects normal or non-overlapping TPC output for each group. — — — — G3NOV G2NOV G1NOV G0NOV Initial value Read/Write — — — — Reserved bits Group 3 non-overlap Selects non-overlapping TPC output for group 3 (TP to TP )
Page 353 Bit 3—Group 3 Non-Overlap (G3NOV): Selects normal or non-overlapping TPC output for group 3 (TP to TP Bit 3 G3NOV Description Normal TPC output in group 3 (output values change at (Initial value) compare match A in the selected 16-bit timer channel) Non-overlapping TPC output in group 3 (independent 1 and 0 output at compare match A and B in the selected 16-bit timer channel) Bit 2—Group 2 Non-Overlap (G2NOV): Selects normal or non-overlapping TPC output for...
Page 354: Operation
10.3 Operation 10.3.1 Overview When corresponding bits in PADDR or PBDDR and NDERA or NDERB are set to 1, TPC output is enabled. The TPC output initially consists of the corresponding PADR or PBDR contents. When a compare-match event selected in TPCR occurs, the corresponding NDRA or NDRB bit contents are transferred to PADR or PBDR to update the output values.
Page 355: Output Timing
10.3.2 Output Timing If TPC output is enabled, NDRA/NDRB contents are transferred to PADR/PBDR and output when the selected compare match event occurs. Figure 10.3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. φ...
Page 356: Normal Tpc Output
10.3.3 Normal TPC Output Sample Setup Procedure for Normal TPC Output: Figure 10.4 shows a sample procedure for setting up normal TPC output. Normal TPC output Set TIOR to make GRA an output compare Select GR functions register (with output inhibited). Set GRA value Set the TPC output trigger period.
Page 357 Example of Normal TPC Output (Example of Five-Phase Pulse Output): Figure 10.5 shows an example in which the TPC is used for cyclic five-phase pulse output. TCNT value Compare match TCNT H'0000 Time NDRB PBDR The 16-bit timer channel to be used as the output trigger channel is set up so that GRA is an output compare register and the counter will be cleared by compare match A.
Page 358: Non-Overlapping Tpc Output
10.3.4 Non-Overlapping TPC Output Sample Setup Procedure for Non-Overlapping TPC Output: Figure 10.6 shows a sample procedure for setting up non-overlapping TPC output. Non-overlapping TPC output Select GR functions Set TIOR to make GRA and GRB output compare registers (with output inhibited). Set GR values Set the TPC output trigger period in GRB 16-bit timer...
Page 359 Example of Non-Overlapping TPC Output (Example of Four-Phase Complementary Non- Overlapping Output): Figure 10.7 shows an example of the use of TPC output for four-phase complementary non-overlapping pulse output. TCNT value TCNT H'0000 Time NDRB PBDR Non-overlap margin The 16-bit timer channel to be used as the output trigger channel is set up so that GRA and GRB are output compare registers and the counter will be cleared by compare match B.
Page 360: Tpc Output Triggering By Input Capture
10.3.5 TPC Output Triggering by Input Capture TPC output can be triggered by 16-bit timer input capture as well as by compare match. If GRA functions as an input capture register in the 16-bit timer channel selected in TPCR, TPC output will be triggered by the input capture signal.
Page 361: Usage Notes
10.4 Usage Notes 10.4.1 Operation of TPC Output Pins to TP are multiplexed with 16-bit timer, address bus, and other pin functions. When 16-bit timer, or address bus output is enabled, the corresponding pins cannot be used for TPC output. The data transfer from NDR bits to DR bits takes place, however, regardless of the usage of the pin.
Page 362 Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A. NDR contents should not be altered during the interval from compare match B to compare match A (the non-overlap margin). This can be accomplished by having the IMFA interrupt service routine write the next data in NDR.
Page 363: Section 11 Watchdog Timer
As a watchdog timer, it generates a reset signal for the H8/3062 chip if a system crash allows the timer counter (TCNT) to overflow before being rewritten. In interval timer operation, an interval timer interrupt is requested at each TCNT overflow.
Page 364: Block Diagram
11.1.2 Block Diagram Figure 11.1 shows a block diagram of the WDT. Overflow Internal TCNT data bus Read/ Interrupt Interrupt signal write control (interval timer) control TCSR Internal clock sources φ/2 RSTCSR φ/32 φ/64 Reset Reset control Clock φ/128 (internal, external) Clock φ/256 selector...
Page 365: Register Configuration
11.1.4 Register Configuration Table 11.2 summarizes the WDT registers. Table 11.2 WDT Registers Address* Write* Read Name Abbreviation Initial Value H'FFF8C H'FFF8C Timer control/status register TCSR R/(W)* H'18 H'FFF8D Timer counter TCNT H'00 H'FFF8E H'FFF8F Reset control/status register RSTCSR R/(W)* H'3F Notes: 1.
Page 366: Timer Control/Status Register (Tcsr)
11.2.2 Timer Control/Status Register (TCSR) TCSR is an 8-bit readable and writable register. Its functions include selecting the timer mode and clock source. WT/IT — — CKS2 CKS1 CKS0 Initial value Read/Write R/(W) — — Clock select These bits select the TCNT clock source Reserved bits Timer enable...
Page 367 Bit 6—Timer Mode Select (WT/IT): Selects whether to use the WDT as a watchdog timer or interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request when TCNT overflows. If used as a watchdog timer, the WDT generates a reset signal when TCNT overflows.
Page 368: Reset Control/Status Register (Rstcsr)
Bit 7—Watchdog Timer Reset (WRST): During watchdog timer operation, this bit indicates that TCNT has overflowed and generated a reset signal. This reset signal resets the entire H8/3062 chip internally. If bit RSTOE is set to 1, this reset signal is also output (low) at the RESO pin to initialize external system devices.
Page 369: Notes On Register Access
Bit 6—Reset Output Enable (RSTOE): Enables or disables external output at the RESO pin of the reset signal generated if TCNT overflows during watchdog timer operation. Note that there is no RESO pin in the versions with on-chip flash memory. Bit 6 RSTOE Description Reset signal is not output externally...
Page 370 Writing to RSTCSR: RSTCSR must be written by a word transfer instruction. It cannot be written by byte transfer instructions. Figure 11.3 shows the format of data written to RSTCSR. To write 0 in the WRST bit, the write data must have H'A5 in the upper byte and H'00 in the lower byte.
Page 371: Operation
TCNT value (normally by writing H'00) before overflow occurs. If TCNT fails to be rewritten and overflows due to a system crash etc., the H8/3062 is internally reset for a duration of 518 states. The watchdog reset signal can be externally output from the RESO pin to reset external system devices.
Page 372: Timing Of Setting Of Overflow Flag (Ovf)
11.3.2 Interval Timer Operation Figure 11.5 illustrates interval timer operation. To use the WDT as an interval timer, clear bit WT/IT to 0 and set bit TME to 1 in TCSR. An interval timer interrupt request is generated at each TCNT overflow.
Page 373: Timing Of Setting Of Watchdog Timer Reset Bit (Wrst)
1 when TCNT overflows and OVF is set to 1. At the same time an internal reset signal is generated for the entire H8/3062 chip. This internal reset signal clears OVF to 0, but the WRST bit remains set to 1. The reset routine must therefore clear the WRST bit.
Page 374: Interrupts
11.4 Interrupts During interval timer operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. 11.5 Usage Notes Contention between TCNT Write and Increment: If a timer counter clock pulse is generated during the T state of a write cycle to TCNT, the write takes priority and the timer count is not incremented.
Page 375: Section 12 Serial Communication Interface
12.1 Overview The H8/3062 Series has a serial communication interface (SCI) with two independent channels. The two channels have identical functions. The SCI can communicate in both asynchronous and synchronous mode. It also has a multiprocessor communication function for serial communication among two or more processors.
Page 376 • Full-duplex communication The transmitting and receiving sections are independent, so the SCI can transmit and receive simultaneously. The transmitting and receiving sections are both double-buffered, so serial data can be transmitted and received continuously. • The following settings can be made for the serial data to be transferred: ...
Page 377: Block Diagram
12.1.2 Block Diagram Figure 12.1 shows a block diagram of the SCI. Module data bus Internal data bus φ Baud rate φ/ 4 SCMR generator φ/16 Transmit/receive φ/64 control Parity generate Clock Parity check External clock T E I T X I R X I E R I Legend:...
Page 378: Pin Configuration
12.1.3 Pin Configuration The SCI has serial pins for each channel as listed in table 12.1. Table 12.1 SCI Pins Channel Name Abbreviation Function Serial clock pin Input/output clock input/output Receive data pin Input receive data input Transmit data pin Output transmit data output Serial clock pin...
Page 379: Register Configuration
12.1.4 Register Configuration The SCI has internal registers as listed in table 12.2. These registers select asynchronous or synchronous mode, specify the data format and bit rate, control the transmitter and receiver sections, and specify switching between the serial communication interface and smart card interface.
Page 380: Register Descriptions
12.2 Register Descriptions 12.2.1 Receive Shift Register (RSR) RSR is the register that receives serial data. — — — — — — — — Read/Write The SCI loads serial data input at the RxD pin into RSR in the order received, LSB (bit 0) first, thereby converting the data to parallel data.
Page 381: Transmit Shift Register (Tsr)
12.2.3 Transmit Shift Register (TSR) TSR is the register that transmits serial data. — — — — — Read/Write — — — The SCI loads transmit data from TDR to TSR, then transmits the data serially from the TxD pin, LSB (bit 0) first.
Page 382: Serial Mode Register (Smr)
12.2.5 Serial Mode Register (SMR) SMR is an 8-bit register that specifies the SCI's serial communication format and selects the clock source for the baud rate generator. STOP CKS1 CKS0 Initial value Read/Write Clock select 1/0 These bits select the baud rate generator's clock source Multiprocessor mode...
Page 383 Bit 7 Description Asynchronous mode (Initial value) Synchronous mode For Smart Card Interface (SMIF Bit in SCMR Set to 1): Selects GSM mode for the smart card interface. Bit 7 Description The TEND flag is set 12.5 etu after the start bit (Initial value) The TEND flag is set 11.0 etu after the start bit Note: etu: Elementary time unit (time required to transmit one bit)
Page 384 Bit 4 Description Even parity* (Initial value) Odd parity* Notes: 1. When even parity is selected, the parity bit added to transmit data makes an even number of 1s in the transmitted character and parity bit combined. Receive data must have an even number of 1s in the received character and parity bit combined.
Page 385: Serial Control Register (Scr)
For the relationship between the clock source, bit rate register setting, and baud rate, see section 12.2.8, Bit Rate Register (BRR). Bit 1 Bit 0 CKS1 CKS0 Description φ (Initial value) φ/4 φ/16 φ/64 12.2.6 Serial Control Register (SCR) SCR register enables or disables the SCI transmitter and receiver, enables or disables serial clock output in asynchronous mode, enables or disables interrupts, and selects the transmit/receive clock source.
Page 386 The CPU can always read and write SCR. SCR is initialized to H'00 by a reset and in standby mode. Bit 7—Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt (TXI) requested when the TDRE flag in SSR is set to 1 due to transfer of serial transmit data from TDR to TSR.
Page 387 Bit 4 Description Receiving disabled* (Initial value) Receiving enabled* Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags. These flags retain their previous values. 2. In the enabled state, serial receiving starts when a start bit is detected in asynchronous mode, or serial clock input is detected in synchronous mode.
Page 388 For serial communication interface (SMIF bit in SCMR cleared to 0): These bits select the SCI clock source and enable or disable clock output from the SCK pin. Depending on the settings of CKE1 and CKE0, the SCK pin can be used for generic input/output, serial clock output, or serial clock input.
Page 389: Serial Status Register (Ssr)
12.2.7 Serial Status Register (SSR) SSR is an 8-bit register containing multiprocessor bit values, and status flags that indicate the operating status of the SCI. TDRE RDRF ORER FER/ERS TEND MPBT Initial value R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Read/Write Multiprocessor bit transfer Value of multiprocessor bit to be transmitted Multiprocessor bit...
Page 390 The CPU can always read and write SSR, but cannot write 1 in the TDRE, RDRF, ORER, PER, and FER flags. These flags can be cleared to 0 only if they have first been read while set to 1. The TEND and MPB flags are read-only bits that cannot be written. SSR is initialized to H'84 by a reset and in standby mode.
Page 391 Bit 5—Overrun Error (ORER): Indicates that data reception ended abnormally due to an overrun error. Bit 5 ORER Description Receiving is in progress or has ended normally* (Initial value) [Clearing conditions] • The chip is reset or enters standby mode •...
Page 392 For Smart Card Interface (SMIF Bit in SCMR Set to 1): Indicates the status of the error signal sent back from the receiving side during transmission. Framing errors are not detected in smart card interface mode. Bit 4 Description Normal reception, no error signal* (Initial value) [Clearing conditions] •...
Page 393 Bit 2 TEND Description Transmission is in progress [Clearing condition] Read TDRE when TDRE = 1, then write 0 in TDRE End of transmission (Initial value) [Setting conditions] • The chip is reset or enters standby mode • The TE bit in SCR is cleared to 0 •...
Page 394: Bit Rate Register (Brr)
Bit 0—Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit added to transmit data when a multiprocessor format in selected for transmitting in asynchronous mode. The MPBT bit setting is ignored in synchronous mode, when a multiprocessor format is not selected, or when the SCI cannot transmit.
Page 395 Table 12.3 Examples of Bit Rates and BRR Settings in Asynchronous Mode φ (MHz) 2.097152 2.4576 Bit Rate (bit/s) Error (%) n Error (%) n Error (%) n Error (%) 141 0.03 148 -0.04 174 -0.26 212 0.03 103 0.16 108 0.21 127 0.00 155 0.16...
Page 396 φ (MHz) 6.144 7.3728 Bit Rate (bit/s) Error (%) n Error (%) n Error (%) n Error (%) 106 -0.44 108 0.08 130 -0.07 141 0.03 0.16 0.00 0.00 103 0.16 155 0.16 159 0.00 191 0.00 207 0.16 0.16 0.00 0.00 103 0.16...
Page 397 φ (MHz) 14.7456 Bit Rate (bit/s) Error (%) n Error (%) n Error (%) n Error (%) 230 -0.08 248 -0.17 0.70 0.03 168 0.16 181 0.16 191 0.00 207 0.16 -0.43 0.16 0.00 103 0.16 168 0.16 181 0.16 191 0.00 207 0.16 1200...
Page 398 Table 12.4 Examples of Bit Rates and BRR Settings in Synchronous Mode φ (MHz) Rate (bit/s) n — — — — — — — — — — — — — — — — 124 2 249 3 124 — — 202 3 249 —...
Page 399 The BRR setting is calculated as follows: Asynchronous mode: φ × 10 – 1 64 × 2 × B 2n–1 Synchronous mode: φ × 10 – 1 8 × 2 × B 2n–1 B: Bit rate (bit/s) N: BRR setting for baud rate generator (0 ≤ N ≤ 255) φ: System clock frequency (MHz) n: Baud rate generator input clock (n = 0, 1, 2, 3) (For the clock sources and values of n, see the following table.)
Page 400 Table 12.5 shows the maximum bit rates in asynchronous mode for various system clock frequencies. Tables 12.6 and 12.7 show the maximum bit rates with external clock input. Table 12.5 Maximum Bit Rates for Various Frequencies (Asynchronous Mode) Settings φ (MHz) Maximum Bit Rate (bit/s) 62500 2.097152...
Page 401 Table 12.6 Maximum Bit Rates with External Clock Input (Asynchronous Mode) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 0.7500 46875 3.6864 0.9216 57600 1.0000 62500 4.9152 1.2288 76800 1.2500 78125 1.5000 93750...
Page 402: Operation
Table 12.7 Maximum Bit Rates with External Clock Input (Synchronous Mode) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) 0.3333 333333.3 0.6667 666666.7 1.0000 1000000.0 1.3333 1333333.3 1.6667 1666666.7 2.0000 2000000.0 2.3333 2333333.3 2.6667 2666666.7 3.0000 3000000.0 3.3333 3333333.3 4.1667 4166666.7...
Page 403 Asynchronous Mode • Data length is selectable: 7 or 8 bits • Parity and multiprocessor bits are selectable, and so is the stop bit length (1 or 2 bits). These selections determine the communication format and character length. • In receiving, it is possible to detect framing errors, parity errors, overrun errors, and the break state.
Page 404 Table 12.8 SMR Settings and Serial Communication Formats SMR Settings SCI Communication Format Multi- pro- Bit 7 Bit 6 Bit 2 Bit 5 Bit 3 Data cessor Parity Stop Bit STOP Mode Length Length Asyn- 8-bit data Absent Absent 1 bit chronous 2 bits mode...
Page 405: Operation In Asynchronous Mode
12.3.2 Operation in Asynchronous Mode In asynchronous mode, each transmitted or received character begins with a start bit and ends with one or two stop bits. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCI are independent, so full-duplex communication is possible.
Page 406 Table 12.10 Serial Communication Formats (Asynchronous Mode) SMR Settings Serial Communication Format and Frame Length STOP 8-bit data STOP 8-bit data STOP STOP 8-bit data STOP 8-bit data STOP STOP 7-bit data STOP 7-bit data STOP STOP 7-bit data STOP 7-bit data STOP STOP...
Page 407 Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in SMR and bits CKE1 and CKE0 in SCR. For details of SCI clock source selection, see table 12.9.
Page 408 Figure 12.4 shows a sample flowchart for initializing the SCI. Start of initialization Set the clock source in SCR. Clear the Clear TE and RE bits RIE, TIE, TEIE, MPIE, TE, and RE bits to to 0 in SCR 0. If clock output is selected in asynchronous mode, clock output starts Set CKE1 and CKE0 bits in SCR immediately after the setting is made in...
Page 409 • Transmitting Serial Data (Asynchronous Mode): Figure 12.5 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. SCI initialization: Initialize the transmit data output function of the TxD pin is selected automatically. Start transmitting After the TE bit is set to 1, one frame of 1s is output, then transmission is possible.
Page 410 In transmitting serial data, the SCI operates as follows: • The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. •...
Page 411 • Receiving Serial Data (Asynchronous Mode): Figure 12.7 shows a sample flowchart for receiving serial data and indicates the procedure to follow. SCI initialization: Initialize the receive data input function of the RxD pin is selected automatically. Start receiving (2)(3) Receive error handling and break detection: if a receive error occurs, read the ORER, Read ORER, PER, and FER...
Page 412 Error handling ORER= 1 Overrun error handling FER= 1 Break? Framing error handling Clear RE bit to 0 in SCR PER= 1 Parity error handling Clear ORER, PER, and FER flags to 0 in SSR <End> Figure 12.7 Sample Flowchart for Receiving Serial Data (cont)
Page 413 In receiving, the SCI operates as follows: • The SCI monitors the communication line. When it detects a start bit (0 bit), the SCI synchronizes internally and starts receiving. • Receive data is stored in RSR in order from LSB to MSB. •...
Page 414: Multiprocessor Communication
Figure 12.8 shows an example of SCI receive operation in asynchronous mode. Start Parity Stop Start Parity Stop Data Data Idle (mark) state RDRF RXI interrupt RXI interrupt handler request Framing error, reads data in RDR and ERI interrupt clears RDRF flag to 0 1 frame request Figure 12.8 Example of SCI Receive Operation...
Page 415 Communication Formats: Four formats are available. Parity bit settings are ignored when a multiprocessor format is selected. For details see table 12.10. Clock: See the description of asynchronous mode. Transmitting processor Serial communication line Receiving Receiving Receiving Receiving processor A processor B processor C processor D...
Page 416 Initialize SCI initialization: the transmit data output function of the TxD pin is selected automatically. Start transmitting SCI status check and transmit data write: Read TDRE flag in SSR read SSR, check that the TDRE flag is 1, then write transmit data in TDR. Also set the MPBT flag to 0 or 1 in SSR.
Page 417 In transmitting serial data, the SCI operates as follows: • The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. •...
Page 418 SCI initialization: Initialize the receive data input function of the RxD pin is selected automatically. Start receiving ID receive cycle: set the MPIE bit to 1 in SCR. Set MPIE bit to 1 in SCR SCI status check and ID check: Read ORER and FER flags read SSR, check that the RDRF flag in SSR...
Page 419 Error handling ORER= 1 Overrun error handling FER= 1 Break? Clear RE bit to 0 in SCR Framing error handling Clear ORER, PER, and FER flags to 0 in SSR <End> Figure 12.12 Sample Flowchart for Receiving Multiprocessor Serial Data (cont)
Page 420 Figure 12.13 shows an example of SCI receive operation using a multiprocessor format. Start Stop Start Stop Data (ID1) Data (data1) Idle (mark) state MPIE RDRF RDR value RXI interrupt request RXI interrupt handler reads Not own ID, so MPIE No RXI interrupt MPB detection (multiprocessor interrupt)
Page 421: Synchronous Operation
12.3.4 Synchronous Operation In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver share the same clock but are otherwise independent, so full- duplex communication is possible.
Page 422 Transmitting and Receiving Data: • SCI Initialization (Synchronous Mode): Before transmitting or receiving data, clear the TE and RE bits to 0 in SCR, then initialize the SCI as follows. When changing the communication mode or format, always clear the TE and RE bits to 0 before following the procedure given below.
Page 423 • Transmitting Serial Data (Synchronous Mode): Figure 12.16 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. SCI initialization: the transmit data Initialize output function of the TxD pin is selected automatically. Start transmitting SCI status check and transmit data write: read SSR, check that the TDRE Read TDRE flag in SSR flag is 1, then write transmit data in...
Page 424 In transmitting serial data, the SCI operates as follows. • The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. •...
Page 425 Initialize SCI initialization: the receive data input function of the RxD pin is selected automatically. Start receiving Receive error handling: if a receive (2)(3) error occurs, read the ORER flag in Read ORER flag in SSR SSR, then after executing the necessary error handling, clear the ORER flag to 0.
Page 426 Error handling Overrun error handling Clear ORER flag to 0 in SSR <End> Figure 12.18 Sample Flowchart for Serial Receiving (cont) In receiving, the SCI operates as follows: • The SCI synchronizes with serial clock input or output and synchronizes internally. •...
Page 427 Figure 12.19 shows an example of SCI receive operation. Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER RXI interrupt RXI interrupt handler RXI interrupt Overrun error, request reads data in RDR and request ERI interrupt clears RDRF flag to 0...
Page 428 • Transmitting and Receiving Data Simultaneously (Synchronous Mode): Figure 12.20 shows a sample flowchart for transmitting and receiving serial data simultaneously and indicates the procedure to follow. Initialize SCI initialization: the transmit data output function of the TxD pin and the read data input function of the TxD pin are selected, enabling simultaneous Start of transmitting and receiving transmitting and receiving.
Page 429: Sci Interrupts
12.4 SCI Interrupts The SCI has four interrupt request sources: transmit-end interrupt (TEI), receive-error (ERI), receive-data-full (RXI), and transmit-data-empty interrupt (TXI). Table 12.12 lists the interrupt sources and indicates their priority. These interrupts can be enabled or disabled by the TIE, RIE, and TEIE bits in SCR.
Page 430: Usage Notes
12.5 Usage Notes 12.5.1 Notes on Use of SCI Note the following points when using the SCI. TDR Write and TDRE Flag: The TDRE flag in SSR is a status flag indicating the loading of transmit data from TDR to TSR. The SCI sets the TDRE flag to 1 when it transfers data from TDR to TSR.
Page 431 Break Detection and Processing: Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state the input from the RxD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. In the break state the SCI receiver continues to operate, so if the FER flag is cleared to 0 it will be set to 1 again.
Page 432 The receive margin in asynchronous mode can therefore be expressed as shown in equation (1). D – 0.5 (1 + F) × 100% M = (0.5 – ) – (L – 0.5) F – ..(1) Receive margin (%) Ratio of clock frequency to bit rate (N = 16) Clock duty cycle (D = 0 to 1.0)
Page 433 Switching from SCK Pin Function to Port Pin Function: • Problem in Operation: When switching the SCK pin function to the output port function (high- level output) by making the following settings while DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1 (synchronous mode), low-level output occurs for one half-cycle.
Page 434 • Sample Procedure for Avoiding Low-Level Output: As this sample procedure temporarily places the SCK pin in the input state, the SCK/port pin should be pulled up beforehand with an external circuit. With DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1, make the following settings in the order shown.
Page 435: Section 13 Smart Card Interface
Switchover between the normal serial communication interface and the smart card interface is controlled by a register setting. 13.1.1 Features Features of the smart card interface supported by the H8/3062 Series are listed below. • Asynchronous communication  Data length: 8 bits  Parity bit generation and checking ...
Page 436: Block Diagram
13.1.2 Block Diagram Figure 13.1 shows a block diagram of the smart card interface. Internal Module data bus data bus SCMR φ φ/4 Baud rate generator φ/16 Transmission/ φ/64 reception control Parity generation Clock Parity check External clock Legend SCMR: Smart card mode register RSR: Receive shift register RDR:...
Page 437: Register Configuration
13.1.4 Register Configuration The smart card interface has the internal registers listed in table 13.2. The BRR, TDR, and RDR registers have their normal serial communication interface functions, as described in section 12, Serial Communication Interface. Table 13.2 Smart Card Interface Registers Channel Address* Name...
Page 438: Register Descriptions
13.2 Register Descriptions This section describes the new or modified registers and bit functions in the smart card interface. 13.2.1 Smart Card Mode Register (SCMR) SCMR is an 8-bit readable/writable register that selects smart card interface functions. — — — —...
Page 439 Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This function is used in combination with the SDIR bit to communicate with inverse-convention cards.* The SINV bit does not affect the logic level of the parity bit. For parity settings, see section 13.3.4, Register Settings.
Page 440: Serial Status Register (Ssr)
13.2.2 Serial Status Register (SSR) The function of SSR bit 4 is modified in smart card interface mode. This change also causes a modification to the setting conditions for bit 2 (TEND). TDRE RDRF ORER TEND MPBT Initial value Read/Write R/(W)* R/(W)* R/(W)*...
Page 441: Serial Mode Register (Smr)
Bits 3 to 0: These bits operate as in normal serial communication. For details see section 12.2.7, Serial Status Register (SSR). The setting conditions for transmit end (TEND), however, are modified as follows. Bit 2 TEND Description Transmission is in progress [Clearing condition] Software reads TDRE while it is set to 1, then writes 0 in the TDRE flag.
Page 442: Serial Control Register (Scr)
Bit 7 Description Normal smart card interface mode operation • The TEND flag is set 12.5 etu after the beginning of the start bit. • Clock output on/off control only. (Initial value) GSM mode smart card interface mode operation • The TEND flag is set 11.0 etu after the beginning of the start bit.
Page 443: Operation
CLK pin of the smart card. If the smart card uses an internal clock, this connection is unnecessary. The reset signal should be output from one of the H8/3062 Series’ generic ports. In addition to these pin connections. power and ground connections will normally also be...
Page 444: Data Format
Data line Clock line H8/3062 Series Px (port) chip Reset line Smart card Card-processing device Figure 13.2 Smart Card Interface Connection Diagram Note: Setting both TE and RE to 1 without connecting a smart card enables closed transmission/reception, allowing self-diagnosis to be carried out.
Page 445 No parity error Output from transmitting device Parity error Output from transmitting device Output from receiving Legend device Start bit D0 to D7: Data bits Parity bit Error signal Figure 13.3 Smart Card Interface Data Format The operating sequence is as follows. 1.
Page 446: Register Settings
13.3.4 Register Settings Table 13.3 shows a bit map of the registers used in the smart card interface. Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described in this section. Table 13.3 Smart Card Interface Register Settings Register Address Bit 7...
Page 447 In the H8/3062 Series, inversion specified by the SINV bit applies only to the data bits, D7 to D0. For parity bit inversion, the O/E bit in SMR must be set to odd parity mode. This applies...
Page 448: Clock
13.3.5 Clock Only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock for the smart card interface. The bit rate is set with the bit rate register (BRR) and the CKS1 and CKS0 bits in the serial mode register (SMR). The equation for calculating the bit rate is shown below.
Page 449 The following equation calculates the bit rate register (BRR) setting from the operating frequency and bit rate. N is an integer from 0 to 255, specifying the value with the smaller error. φ × 10 – 1 1488 × 2 ×...
Page 450: Transmitting And Receiving Data
13.3.6 Transmitting and Receiving Data Initialization: Before transmitting or receiving data, the smart card interface must be initialized as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. 1. Clear the TE and RE bits to 0 in the serial control register (SCR). 2.
Page 451 For details, see Interrupt Operations in this section. Serial data Guard time (1) GM = 0 TEND 12.5 etu (2) GM = 1 TEND 11.0 etu Figure 13.4 Timing of TEND Flag Setting...
Page 452 Start Initialization Start transmitting FER/ERS = 0? Error handling TEND = 1? Write transmit data in TDR, and clear TDRE flag to 0 in SSR All data transmitted? FER/ERS = 0? Error handling TEND = 1? Clear TE bit to 0 Figure 13.5 Sample Transmission Processing Flowchart...
Page 453 (shift register) 1. Data write Data 1 2. Transfer from TDR to TSR Data 1 Data 1 Data remains in TDR Data 1 I/O signal 3. Serial data output Data 1 output In case of normal transmission: TEND flag is set In case of transmit error: ERS flag is set Steps 2 and 3 above are repeated until the...
Page 454 Start Initialization Start receiving ORER = 0 and PER = 0? Error handling RDRF = 1? Read RDR and clear RDRF flag to 0 in SSR All data received? Clear RE bit to 0 Figure 13.8 Sample Reception Processing Flowchart The above procedure may include interrupt handling.
Page 455 When switching from transmit mode to receive mode, first confirm that the transmit operation has been completed, then start from initialization, clearing TE to 0 and setting RE to 1. The TEND flag can be used to check that the transmit operation has been completed. Fixing Clock Output: When the GM bit is set to 1 in SMR, clock output can be fixed by means of the CKE1 and CKE0 bits in SCR.
Page 456 Examples of Operation in GSM Mode: When switching between smart card interface mode and software standby mode, use the following procedures to maintain the clock duty cycle. • Switching from smart card interface mode to software standby mode 1. Set the P9 data register (DR) and data direction register (DDR) to the values for the fixed output state in software standby mode.
Page 457: Usage Notes
13.4 Usage Notes The following points should be noted when using the SCI as a smart card interface. Receive Data Sampling Timing and Receive Margin in Smart Card Interface Mode: In smart card interface mode, the SCI operates on a base clock with a frequency of 372 times the transfer rate.
Page 458 The receive margin can therefore be expressed as follows. Receive margin in smart card interface mode: D – 0.5 (1 + F) × 100% M = (0.5 – ) – (L – 0.5) F – M: Receive margin (%) N: Ratio of clock frequency to bit rate (N = 372) D: Clock duty cycle (L = 0 to 1.0) L: Frame length (L =10) F: Absolute deviation of clock frequency...
Page 459 TEND Figure 13.13 Retransmission in SCI Transmit Mode The smart card interface installed in the H8/3062 Series supports an IC card (smart card) interface with provision for ISO/IEC7816-3 T=0 (character transmission). Therefore, block transfer operations are not supported (error signal transmission, detection, and automatic data...
Page 460: Section 14 A/D Converter
Section 14 A/D Converter 14.1 Overview The H8/3062 Series includes a 10-bit successive-approximations A/D converter with a selection of up to eight analog input channels. When the A/D converter is not used, it can be halted independently to conserve power. For details see section 19.6, Module Standby Function.
Page 461: Block Diagram
14.1.2 Block Diagram Figure 14.1 shows a block diagram of the A/D converter. Internal Module data bus data bus 10-bit D/A – ø/4 Comparator Analog Control circuit multi- plexer Sample-and- ø/8 hold circuit ADTRG interrupt signal Compare match A0 ADTE 8-bit timer 8TCSR0 Legend:...
Page 462: Pin Configuration
14.1.3 Pin Configuration Table 14.1 summarizes the A/D converter’s input pins. The eight analog input pins are divided into two groups: group 0 (AN to AN ), and group 1 (AN to AN ). AV and AV are the power supply for the analog circuits in the A/D converter.
Page 463: Register Configuration
14.1.4 Register Configuration Table 14.2 summarizes the A/D converter’s registers. Table 14.2 A/D Converter Registers Address* Name Abbreviation Initial Value H'FFFE0 A/D data register A H ADDRAH H'00 H'FFFE1 A/D data register A L ADDRAL H'00 H'FFFE2 A/D data register B H ADDRBH H'00 H'FFFE3...
Page 464: A/D Control/Status Register (Adcsr)
data register are reserved bits that are always read as 0. Table 14.3 indicates the pairings of analog input channels and A/D data registers. The CPU can always read and write the A/D data registers. The upper byte can be read directly, but the lower byte is read through a temporary register (TEMP).
Page 465 ADCSR is an 8-bit readable/writable register that selects the mode and controls the A/D converter. ADCSR is initialized to H'00 by a reset and in standby mode. Bit 7—A/D End Flag (ADF): Indicates the end of A/D conversion. Bit 7 Description [Clearing condition] (Initial value)
Page 466: A/D Control Register (Adcr)
Bit 3—Clock Select (CKS): Selects the A/D conversion time. Clear the ADST bit to 0 before switching the conversion time. Bit 3 Description Conversion time = 134 states (maximum) (Initial value) Conversion time = 70 states (maximum) Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): These bits and the SCAN bit select the analog input channels.
Page 467: Cpu Interface
Bit 7—Trigger Enable (TRGE): Enables or disables starting of A/D conversion by an external trigger or 8-bit timer compare match. Bit 7 TRGE Description Starting of A/D conversion by an external trigger or 8-bit timer (Initial value) compare match is disabled A/D conversion is started at the falling edge of the external trigger signal (ADTRG) or by an 8-bit timer compare match External trigger pin and 8-bit timer selection is performed by the 8-bit timer.
Page 468 Upper-byte read Module data bus Bus interface (H'AA) TEMP (H'40) ADDRnH ADDRnL (H'AA) (H'40) (n = A to D) Lower-byte read Module data bus Bus interface (H'40) TEMP (H'40) ADDRnH ADDRnL (H'AA) (H'40) (n = A to D) Figure 14.2 A/D Data Register Access Operation (Reading H'AA40)
Page 469: Operation
14.4 Operation The A/D converter operates by successive approximations with 10-bit resolution. It has two operating modes: single mode and scan mode. 14.4.1 Single Mode (SCAN = 0) Single mode should be selected when only one A/D conversion on one channel is required. A/D conversion starts when the ADST bit is set to 1 by software, or by external trigger input.
Page 470 Figure 14.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)
Page 471: Scan Mode (Scan = 1)
14.4.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by software or external trigger input, A/D conversion starts on the first channel in the group (AN when CH2 = 0, AN when CH2 = 1).
Page 472 Figure 14.4 Example of A/D Converter Operation (Scan Mode, Channels AN to AN Selected)
Page 473: Input Sampling And A/D Conversion Time
14.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time t after the ADST bit is set to 1, then starts conversion. Figure 14.5 shows the A/D conversion timing.
Page 474: External Trigger Input Timing
Table 14.4 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1 Symbol Synchronization delay — — Input sampling time — — — — A/D conversion time — — CONV Note: Values in the table are numbers of states. 14.4.4 External Trigger Input Timing A/D conversion can be externally triggered When the TRGE bit is set to 1 in ADCR and the 8-bit...
Page 475: Interrupts
14.5 Interrupts The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt request can be enabled or disabled by the ADIE bit in ADCSR. 14.6 Usage Notes When using the A/D converter, note the following points: 1.
Page 476 100 Ω to AN 0.1 µF Notes: 1. 10 µF 0.01 µF 2. Rin: input impedance Figure 14.7 Example of Analog Input Protection Circuit Table 14.5 Analog Input Pin Ratings Item Unit Analog input capacitance — Allowable signal-source impedance — kΩ...
Page 477 6. A/D Conversion Accuracy Definitions A/D conversion accuracy in the H8/3062 Series is defined as follows: • Resolution Digital output code length of A/D converter • Offset error Deviation from ideal A/D conversion characteristic of analog input voltage required to raise digital output from minimum voltage value 0000000000 to 0000000001 (figure 14.10)
Page 478 Figure 14.10 A/D Converter Accuracy Definitions (2) 7. Allowable Signal-Source Impedance The analog inputs of the H8/3062 Series are designed to assure accurate conversion of input signals with a signal-source impedance not exceeding 10 kΩ. The reason for this rating is that it enables the input capacitor in the sample-and-hold circuit in the A/D converter to charge within the sampling time.
Page 479 H8/3062 Series Equivalent circuit of A/D converter Sensor output impedance 10 kΩ Up to 10 kΩ Sensor input Cin = Low-pass 20 pF 15 pF filter C Up to 0.1 µF Figure 14.11 Analog Input Circuit (Example)
Page 480: Section 15 D/A Converter
Section 15 D/A Converter 15.1 Overview The H8/3062 Series includes a D/A converter with two channels. 15.1.1 Features D/A converter features are listed below. • Eight-bit resolution • Two output channels • Conversion time: maximum 10 µs (with 20-pF capacitive load) •...
Page 481: Block Diagram
15.1.2 Block Diagram Figure 15.1 shows a block diagram of the D/A converter. Internal Module data bus data bus 8-bit D/A Control circuit Legend: DACR: D/A control register DADR0: D/A data register 0 DADR1: D/A data register 1 DASTCR: D/A standby control register Figure 15.1 D/A Converter Block Diagram...
Page 482: Pin Configuration
15.1.3 Pin Configuration Table 15.1 summarizes the D/A converter's input and output pins. Table 15.1 D/A Converter Pins Pin Name Abbreviation I/O Function Analog power supply pin Input Analog power supply and reference voltage Analog ground pin Input Analog ground and reference voltage Analog output pin 0 Output Analog output, channel 0...
Page 483: Register Descriptions
15.2 Register Descriptions 15.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1) Initial value Read/Write The D/A data registers (DADR0 and DADR1) are 8-bit readable/writable registers that store the data to be converted. When analog output is enabled, the D/A data register values are constantly converted and output at the analog output pins.
Page 484 Bit 7—D/A Output Enable 1 (DAOE1): Controls D/A conversion and analog output. Bit 7 DAOE1 Description analog output is disabled Channel-1 D/A conversion and DA analog output are enabled Bit 6—D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output. Bit 6 DAOE0 Description...
Page 485: D/A Standby Control Register (Dastcr)
15.2.3 D/A Standby Control Register (DASTCR) DASTCR is an 8-bit readable/writable register that enables or disables D/A output in software standby mode. — — — — — — — DASTE Initial value Read/Write — — — — — — — Reserved bits D/A standby enable Enables or disables D/A output...
Page 486 An example of D/A conversion on channel 0 is given next. Timing is indicated in figure 15.2. 1. Data to be converted is written in DADR0. 2. Bit DAOE0 is set to 1 in DACR. D/A conversion starts and DA becomes an output pin.
Page 487: D/A Output Control
15.4 D/A Output Control In the H8/3062 Series, D/A converter output can be enabled or disabled in software standby mode. When the DASTE bit is set to 1 in DASTCR, D/A converter output is enabled in software standby mode. The D/A converter registers retain the values they held prior to the transition to software standby mode.
Page 488: Section 16 Ram
16.1 Overview The H8/3062 Series has high-speed static RAM on-chip. The RAM is connected to the CPU by a 16-bit data bus. The CPU accesses both byte data and word data in two states, making the RAM useful for rapid data transfer.
Page 489: Block Diagram
Even addresses Odd addresses Legend: SYSCR: System control register Note: * This example is of the H8/3062 mask ROM version operating in mode 7. The lower 20 bits of the address are shown. Figure 16.1 RAM Block Diagram 16.1.2 Register Configuration The on-chip RAM is controlled by SYSCR.
Page 490: System Control Register (Syscr)
16.2 System Control Register (SYSCR) SSBY STS2 STS1 STS0 NMIEG SSOE RAME Initial value Read/Write RAM enable bit Enables or disables on-chip RAM Software standby output port enable NMI edge select User bit enable Standby timer select 2 to 0 Software standby One function of SYSCR is to enable or disable access to the on-chip RAM.
Page 491: Operation
16.3 Operation When the RAME bit is set to 1, the on-chip RAM is enabled. Accesses to the addresses shown in table 16.1 are directed to the on-chip RAM. In modes 1 to 5 (expanded modes), when the RAME bit is cleared to 0, the off-chip address space is accessed. In mode 6, 7 (single-chip mode), when the RAME bit is cleared to 0, the on-chip RAM is not accessed: read access always results in H'FF data, and write access is ignored.
Page 492: Section 17 Rom
The H8/3062F-ZTAT and H8/3062F-ZTAT R-mask version have 128 kbytes of on-chip flash memory. The H8/3062 (mask ROM version) has 128 kbytes of on-chip mask ROM, the H8/3061 (mask ROM version) has 96 kbytes, and the H8/3060 (mask ROM version) has 64 kbytes. The ROM is connected to the CPU by a 16-bit data bus.
Page 493: Overview Of Flash Memory (H8/3062F-Ztat, H8/3062F-Ztat R-Mask Version)
17.2 Overview of Flash Memory (H8/3062F-ZTAT, H8/3062F-ZTAT R-Mask Version) 17.2.1 Features The features of the flash memory in the H8/3062F-ZTAT and H8/3062F-ZTAT R-mask version are summarized below. • Four flash memory operating modes  Program mode  Erase mode  Program-verify mode ...
Page 494: Block Diagram
17.2.2 Block Diagram Figure 17.1 shows a block diagram of the flash memory. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) FLMCR Operating FWE pin* Bus interface/controller mode Mode pins RAMCR FLMSR H'00000 H'00001 H'00002 H'00003 On-chip Flash memory (128 kbytes) H'1FFFC...
Page 495: Pin Configuration
17.2.3 Pin Configuration The flash memory is controlled by means of the pins shown in table 17.2. Table 17.2 Flash Memory Pins Pin Name Abbreviation Function Reset Input Reset Flash write enable FWE* Input Flash program/erase protection by hardware Mode 2 Input Sets operating mode of H8/3062F-ZTAT or H8/3062F-ZTAT R-mask version...
Page 496: Flash Memory Register Descriptions
17.3 Flash Memory Register Descriptions 17.3.1 Flash Memory Control Register (FLMCR) FLMCR is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode is entered by setting SWE to 1 when FWE = 1, then setting the corresponding bit.
Page 497 Bit 7—Flash Write Enable (FWE): Sets hardware protection against flash memory programming/erasing. See section 17.9, Flash Memory Programming and Erasing Precautions, for more information on the use of this bit. Bit 7 Description When a low level is input to the FWE pin (hardware-protected state) When a high level is input to the FWE pin Bit 6—Software Write Enable (SWE)* : Enables or disables flash memory programming and...
Page 498 Bit 3—Erase-Verify Mode (EV)* : Selects erase-verify mode transition or clearing. (Do not set the SWE, ESU, PSU, PV, E, or P bit at the same time.) Bit 3 Description Erase-verify mode cleared (Initial value) Transition to erase-verify mode [Setting condition] When FWE = 1 and SWE = 1 Bit 2—Program-Verify Mode (PV)* : Selects program-verify mode transition or clearing.
Page 499: Erase Block Register (Ebr)
Notes: 1. Do not set multiple bits simultaneously. Do not cut V when a bit is set. 2. The SWE bit must not be set or cleared at the same time as other bits (ESU, PSU, EV, PV, E, or P). 3.
Page 500 Table 17.4 Flash Memory Erase Blocks Block (Size) Address EB0 (1 kbyte) H'000000–H'0003FF EB1 (1 kbyte) H'000400–H'0007FF EB2 (1 kbyte) H'000800–H'000BFF EB3 (1 kbyte) H'000C00–H'000FFF EB4 (28 kbytes) H'001000–H'007FFF EB5 (32 kbytes) H'008000–H'00FFFF EB6 (32 kbytes) H'010000–H'017FFF EB7 (32 kbytes) H'018000–H'01FFFF 17.3.3 RAM Control Register (RAMCR)
Page 501 Bits 2 and 1—RAM2 and RAM1: These bits are used with bit 3 to reassign an area to RAM (see table 17.5). The initial setting for this bit is 0 in modes 5, 6, and 7 (internal flash memory enabled) and programming is enabled.* In modes other than 5 to 7, 0 is always read and writing is disabled.
Page 502 17.3.4 Flash Memory Status Register (FLMSR) FLMSR is used to detect flash memory errors. FLER — — — — — — — Initial value — — — — — — Read/Write — Reserved bits Flash memory error (FLER) Status flag indicating detection of an error during flash memory programming or erasing Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during flash memory programming or erasing.
Page 503 17.4 On-Board Programming Mode When pins are set to on-board programming mode and a reset-start is executed, the chip enters the on-board programming state in which on-chip flash memory programming, erasing, and verifying can be carried out. There are two operating modes in this mode—boot mode and user program mode—set by the mode pins (MD –MD ) and the FWE pin.
Page 504 On-Board Programming Modes • Boot mode 1. Initial state 2. Programming control program transfer The flash memory is in the erased state when the When boot mode is entered, the boot program in device is shipped. The description here applies to the H8/3062F-ZTAT or H8/3062F-ZTAT R-mask the case where the old program version or data version (originally incorporated in the chip) is...
Page 505 • User program mode 1. Initial state 2. Programming/erase control program transfer (1) The program that will transfer the When the FWE pin is driven high, user software programming/ erase control program to on-chip confirms this fact, executes the transfer program RAM should be written into the flash memory by in the flash memory, and transfers the the user beforehand.
Page 506 17.4.1 Boot Mode When boot mode is used, a flash memory programming control program must be prepared beforehand in the host, and SCI channel 1, which is to be used, must be set to asynchronous mode. When a reset-start is executed after setting the pins of the H8/3062F-ZTAT or H8/3062F-ZTAT R-mask version to boot mode, the boot program already incorporated in the MCU is activated, the low period of the data sent from the host is first measured, and the bit rate register (BRR) value determined.
Page 507 1. Set the MCU to boot mode and execute reset-start. Start 2. Set the host to the prescribed bit rate (4800/9600) and have it transmit H'00 data continuously using a Set pins to boot mode and transfer data format of 8-bit data plus 1 stop bit. execute reset-start 3.
Page 508 Automatic SCI Bit Rate Adjustment: Start Stop Low period (9 bits) measured (H'00 data) High period (1 or more bits) Figure 17.7 Measurement of Low Period of Host’s Transmit Data When boot mode is initiated, the MCU measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host (figure 17.7).
Page 509 On-Chip RAM Area Divisions in Boot Mode: In boot mode, the RAM area is divided into an area used by the boot program and an area to which the user program is transferred via the SCI, as shown in figure 17.8. The boot program area becomes available when a transition is made to the execution state for the user program transferred to RAM.
Page 510 since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area must be specified for use by the user program. The initial values of other on-chip registers are not changed. 6. Boot mode can be entered by setting pins MD to MD and FWE in accordance with the mode setting conditions shown in table 17.6, and then executing a reset-start.
Page 511 3. See section 4.2.2, Reset Sequence, and section 17.9, Flash Memory Programming and Erasing Precautions. The reset period during operation is a minimum of 10 system clock cycles for the H8/3062, H8/3061, and H8/3060 (versions with on-chip mask ROM), but a minimum of 20 system clock cycles for the H8/3062F-ZTAT and the H8/3062F-ZTAT R-mask version.
Page 512 Procedure: MD2–MD0 = 101, 111 A program that executes operations 3 to 8 below must be written into flash memory by the user beforehand. Reset-start 1. Set the mode pins to an on-chip ROM enabled mode (mode 5 or 7). 2.
Page 513 17.5 Flash Memory Programming/Erasing A software method, using the CPU, is employed to program and erase flash memory in the on- board programming modes. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes are made by setting the PSU, ESU, P, E, PV, and EV bits in FLMCR.
Page 514 E = 1 Erase setup Erase mode state E = 0 ESU = 1 Normal mode ESU = 0 FWE = 1 FWE = 0 Erase-verify EV = 1 mode On-board SWE = 1 EV = 0 Software programming mode programming Software programming enable...
Page 515 Following the elapse of (x) µs or more after the SWE bit is set to 1 in FLMCR, 32-byte data is written consecutively to the write addresses. The lower 8 bits of the first address written to must be H'00, H'20, H'40, H'60, H'80, H'A0, H'C0, or H'E0. Thirty-two consecutive byte data transfers are performed.
Page 516 Start Set SWE bit in FLMCR Wait (x) µsec Store 32-byte write data in write data area and reprogram data area Programming operation counter n ← 1 Notes: 1. Programming should be performed in the erased state. Consecutively write 32-byte data in (Perform 32-byte programming on memory after all 32 bytes reprogram data area in RAM to flash memory have been erased.)
Page 517 17.5.3 Erase Mode When erasing flash memory, the single-block erase flowchart shown in figure 17.12 should be followed. The wait times (x, y, z, α, ß, γ, ε, η) after bits are set or cleared in the flash memory control register (FLMCR) and the maximum number of erase operations (N) are shown in table 22.20 in section 22.2.6, Flash Memory Characteristics.
Page 518 Start Set SWE bit in FLMCR Wait (x) µsec Erase counter n ← 1 Set EBR Enable WDT Set ESU bit in FLMCR Wait (y) µsec Set E bit in FLMCR Start of erase Wait (z) msec Clear E bit in FLMCR End of erase Wait (α) µsec Clear ESU bit in FLMCR...
Page 519 17.6 Flash Memory Protection There are three kinds of flash memory program/erase protection: hardware, software, and error protection. 17.6.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Hardware protection is reset by settings in the flash memory control register (FLMCR) and the erase block register (EBR).
Page 520 Function Item Description Program Erase Verify* • Error protection Possible When a microcomputer operation error possible possible* (error generation (FLER=1)) was detected while flash memory was being programmed/erased, error protection is enabled. At this time, the FLMCR and EBR settings are held, but programming/erasing is aborted at the time the error was generated.
Page 521 17.6.2 Software Protection Software protection can be implemented by setting the RAMS bit in the RAM control register (RAMCR) and the erase block register (EBR). With software protection, setting the P or E bit in the flash memory control register (FLMCR) does not cause a transition to program mode or erase mode.
Page 522 2. For details of FLER bit setting conditions, see section 17.3.4, Flash Memory Status Register (FLMSR). 3. FLMCR and EBR can be written to. However, registers will be initialized if a transition is made to software standby mode in the error protection state. Memory read verify mode Reset or hardware...
Page 523 To prevent such abnormal operations, therefore, it is necessary to ensure correct operation in accordance with the program/erase algorithm, with the flash write enable (FWE) voltage applied, and to conduct constant monitoring for MCU errors, internally and externally, using the watchdog timer or other means.
Page 524 17.7 Flash Memory Emulation in RAM As flash memory programming and erasing takes time, it may be difficult to carry out tuning by writing parameters and other data in real time. In this case, real-time programming of flash memory can be emulated by overlapping part of RAM (H'FFF000–H'FFF3FF) onto a small block area in flash memory.
Page 525 Notes on Use of Emulation in RAM: 1. Flash write enable (FWE) application and releasing As in on-board program mode, care is required when applying and releasing FWE to prevent erroneous programming or erasing. To prevent erroneous programming and erasing due to program runaway during FWE application, in particular, the watchdog timer should be set when the PSU, P, ESU, or E bit is set to 1 in FLMCR1, even while the emulation function is being used.
Page 526 In PROM mode, the on-chip ROM can be freely programmed using a general-purpose PROM writer that supports the Hitachi microcomputer device type with 128-kbyte on-chip flash memory. 17.8.1 Socket Adapters and Memory Map In PROM mode using a PROM writer, memory reading (verification) and writing and flash memory initialization (total erasure) can be performed.
Page 527 3. The memory is initially in the erased state when the device is shipped by Hitachi. For samples for which the erasure history is unknown, it is recommended that erasing be executed to check and correct the initialization (erase) level.
Page 528 1. Use the specified voltages and timing for programming and erasing. Applied voltages in excess of the rating can permanently damage the device. Use a PROM programmer that supports the Hitachi microcomputer device type with 128-kbyte on-chip flash memory. Do not select the HN28F101 setting for the PROM programmer. An incorrect setting will result in application of a high level to the FWE pin, damaging the device.
Page 529 to another mode, also, a mode programming setup time is necessary with respect to the reset release timing. In a reset during operation, the RES pin must be held low for a minimum of 20 system clock cycles. • In user program mode, FWE can be switched between high and low level regardless of RES input.
Page 530 7. Do not use interrupts while flash memory is being programmed or erased. All interrupt requests, including NMI, should be disabled during FWE application to give priority to program/erase operations (including emulation in RAM). Bus release must also be disabled. 8.
Page 531 Wait time: Programming/ erasing possible φ Min 0 µs OSC1 to MD SWE set SWE cleared SWE bit Period during which flash memory access is prohibited (x: Wait time after setting SWE bit)* Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1.
Page 532 Program- Program- Program- Program- ming/ ming/ ming/ ming/ Wait Wait Wait Wait erasing erasing erasing erasing time: time: time: time: possible possible possible possible φ OSC1 Min 0µs to MD RESW SWE set cleared SWE bit Boot Mode Mode User User program mode User User program...
Page 533 17.10 Mask ROM (H8/3062 Mask ROM Version, H8/3061 Mask ROM Version, H8/3060 Mask ROM Version) Overview 17.10.1 Block Diagram Figure 17.19 shows a block diagram of the ROM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits)
Page 534 17.11 Notes on Ordering Mask ROM Version Chips When ordering H8/3062, H8/3061, and H8/3060 with mask ROM, note the following. 1. When ordering by means of an EPROM, use a 128-kbyte one. 2. Fill all unused addresses with H'FF as shown in figure 17.20 to make the ROM data size 128- kbytes for the H8/3062, H8/3061, and H8/3060 mask ROM versions, which incorporate different sizes of ROM.
Page 535 17.12 Notes when Converting the F-ZTAT Application Software to the Mask-ROM Versions Please note the following when converting the F-ZTAT application software to the mask-ROM versions. The values read from the internal registers for the flash ROM or the mask-ROM version and F- ZTAT version differ as follows.
Page 536 Section 18 Flash Memory [H8/3064F-ZTAT] 18.1 Overview The H8/3064F-ZTAT has 256 kbytes of on-chip flash memory. The flash memory is connected to the CPU by a 16-bit data bus. The CPU accesses both byte data and word data in two states, enabling rapid data transfer.
Page 537 H'FFDF20 to H'FFE71F User area H'FFF400 to H'FFFF1F H'FFE720 to H'FFFF1F PROM mode Use of PROM writer supporting Hitachi Use of PROM writer supporting Hitachi microcomputer device type with 128 microcomputer device type with 256 kbytes on-chip flash memory kbytes on-chip flash memory Notes: 1.
Page 538 18.2 Features The H8/3064F-ZTAT has 256 kbytes of on-chip flash memory. The features of the flash memory are summarized below. • Four flash memory operating modes  Program mode  Erase mode  Program-verify mode  Erase-verify mode • Programming/erase methods The flash memory is programmed 128 bytes at a time.
Page 539 18.2.1 Block Diagram Internal address bus Internal data bus (16 bits) FLMCR1 FLMCR2 Operating FWE pin Bus interface/controller mode Mode pins EBR1 EBR2 RAMCR Flash memory (256 kbytes) Legend FLMCR1: Flash memory control register 1 FLMCR2: Flash memory control register 2 EBR1: Erase block register 1 EBR2:...
Page 540 18.2.2 Pin Configuration The flash memory is controlled by means of the pins shown in table 18.3. Table 18.3 Flash Memory Pins Pin Name Abbreviation Function Reset Input Reset Flash write enable Input Flash program/erase protection by hardware Mode 2 Input Sets H8/3064F-ZTAT operating mode Mode 1...
Page 541 18.3 Register Descriptions 18.3.1 Flash Memory Control Register 1 (FLMCR1) Initial value —* Read/Write Note: * Determined by the state of the FWE pin. FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode for addresses H'00000 to H'3FFFF is entered by setting the SWE bit when FWE = 1, then setting the PV or EV bit.
Page 542 Bit 6—Software Write Enable (SWE): Enables or disables flash memory programming and erasing. (This bit should be set when setting bits 5 to 0, EBR1 bits 7 to 0, and EBR2 bits 3 to 0.) Bit 6 Description Programming/erasing disabled (Initial value) Programming/erasing enabled [Setting condition]...
Page 543 Bit 2—Program-Verify Mode (PV): Selects program-verify mode transition or clearing. (Do not set the SWE, ESU, PSU, EV, E, or P bit at the same time.) Bit 2 Description Program-verify mode cleared (Initial value) Transition to program-verify mode [Setting condition] When FWE = 1 and SWE = 1 Bit 1—Erase Mode (E): Selects erase mode transition or clearing.
Page 544 18.3.2 Flash Memory Control Register 2 (FLMCR2) FLER — — — — — — — Initial value Read/Write FLMCR2 is an 8-bit register used for flash memory operating mode control. FLMCR2 is initialized to H'00 by a reset, and in hardware standby mode and software standby mode. When the on-chip flash memory is disabled, a read will return H'00.
Page 545 18.3.3 Erase Block Register 1 (EBR1) Initial value Read/Write EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE bit in FLMCR1 is not set.
Page 546: Ram Control Register (Ramcr)
Note: Bits 7 to 4 in this register are read-only. These bits must not be set to 1. If bits 7 to 4 are set when an EBR1/EBR2 bit is set, EBR1/EBR2 will be initialized to H'00. Table 18.5 Flash Memory Erase Blocks Block (Size) Addresses EB0 (4 kbytes)
Page 547 Bit 3—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, all flash memory blocks are program/erase-protected. Bit 3 RAMS Description Emulation not selected Program/erase-protection of all flash memory blocks is disabled (Initial value) Emulation selected Program/erase-protection of all flash memory blocks is enabled Bits 2 to 0—Flash Memory Area Selection (RAM2 to RAM0): These bits are used together...
Page 548 18.4 Overview of Operation 18.4.1 Mode Transitions When the mode pins and the FWE pin are set in the reset state and a reset-start is executed, the H8/3064F-ZTAT enters one of the operating modes shown in figure 18.2. In user mode, flash memory can be read but not programmed or erased.
Page 549 Reset state RES = 0 User mode with on-chip ROM RES = 0 enabled RES = 0 RES = 0 FWE = 0 PROM mode User program mode Boot mode On-board programming mode Notes: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory.
Page 550 18.4.2 On-Board Programming Modes Example of Boot Mode Operation 1. Initial state 2. Programming control program transfer The old program version or data remains When boot mode is entered, the boot program written in the flash memory. The user should in the H8/3064F-ZTAT (originally incorporated prepare the programming control program and in the chip) is started and the programming...
Page 551 Example of User Program Mode Operation 1. Initial state 2. Programming/erase control program transfer The FWE assessment program that confirms When user program mode is entered, user that user program mode has been entered, and software recognizes this fact, executes the the program that will transfer the programming/ transfer program in the flash memory, and erase control program from flash memory to...
Page 552 18.4.3 Flash Memory Emulation in RAM In the H8/3064F-ZTAT, flash memory programming can be emulated in real time by overlapping the flash memory with part of RAM (“overlap RAM”). When the emulation block set in RAMCR is accessed while the emulation function is being executed, data written in the overlap RAM is read.
Page 553 Flash memory Program data Overlap RAM Application program (program data) Programming control program Execution state Figure 18.4 Writing Overlap RAM Data in User Program Mode 18.4.4 Block Configuration The flash memory in the H8/3064F-ZTAT is divided into three 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks.
Page 554: On-Board Programming Mode
18.5 On-Board Programming Mode When pins are set to on-board programming mode and a reset-start is executed, the chip enters the on-board programming state in which on-chip flash memory programming, erasing, and verifying can be carried out. There are two operating modes in this mode—boot mode and user program mode.
Page 555: Boot Mode
18.5.1 Boot Mode When boot mode is used, a flash memory programming control program must be prepared beforehand in the host, and SCI channel 1, which is to be used, must be set to asynchronous mode. When a reset-start is executed after setting the H8/3064F-ZTAT’ pins to boot mode, the boot program already incorporated in the MCU is activated, and the programming control program prepared beforehand in the host is transmitted sequentially to the H8/3064F-ZTAT, using the SCI.
Page 556 Start Set pins to boot program mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate H8/3064F-ZTAT measures low period of H'00 data transmitted by host H8/3064F-ZTAT calculates bit rate and sets value in bit rate register After bit rate adjustment, H8/3064F-ZTAT transmits one H'00 data byte to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment...
Page 557 Automatic SCI Bit Rate Adjustment: Start Stop Low period (9 bits) measured (H'00 data) High period (1 or more bits) When boot mode is initiated, the H8/3064F-ZTAT measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as 8-bit data, 1 stop bit, no parity.
Page 558 On-Chip RAM Area Divisions in Boot Mode: In boot mode, the RAM area is divided into an area used by the boot program and an area to which the user program is transferred via the SCI, as shown in figure 18.7. The boot program area becomes available when a transition is made to the execution state for the user program transferred to RAM.
Page 559 The contents of the CPU’s internal general registers are undefined at this time, so these registers must be initialized immediately after branching to the user program. In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area must be specified for use by the user program.
Page 560: User Program Mode
3. See section 4.2.2, Reset Sequence, and section 18.11, Flash Memory Programming and Erasing Precautions. The H8/3064F-ZTAT requires a minimum of 20 system clock cycles for a reset during operation. 18.5.2 User Program Mode When set to user program mode, the H8/3064F-ZTAT can program and erase its flash memory by executing a user program/erase control program.
Page 561 Write FWE assessment program and transfer program (and programming/erase control program if necessary) beforehand –MD = 101 or 111 Reset-start Transfer programming/erase control program to RAM Branch to programming/erase control program in RAM area FWE = high (user program mode) Execute programming/erase control program in RAM (flash memory rewriting)
Page 562: Flash Memory Programming/Erasing
18.6 Flash Memory Programming/Erasing A software method, using the CPU, is employed to program and erase flash memory in the on- board programming modes. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes for addresses H'000000 to H'03FFFF are made by setting the PSU, ESU, P, E, PV, and EV bits in FLMCR1.
Page 563 E = 1 Erase setup Erase mode state E = 0 ESU = 1 Normal mode ESU = 0 FWE = 1 FWE = 0 Erase-verify EV = 1 mode On-board SWE = 1 EV = 0 Software programming mode programming Software programming enable...
Page 564: Program Mode
18.6.1 Program Mode When writing data or programs to flash memory, the program/program-verify flowchart shown in figure 18.10 should be followed. Performing programming operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability.
Page 565: Program-Verify Mode
18.6.2 Program-Verify Mode In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. After the elapse of the given programming time, clear the P bit in FLMCR1, then wait for at least ) µs before clearing the PSU bit to exit program mode.
Page 566 loops in reprogramming processing is guaranteed not to exceed the maximum value of the maximum programming count (N). b. After write pulse application, a verify-read is performed in program-verify mode, and programming is judged to have been completed for bits read as 0. The following processing is necessary for programmed bits.
Page 567 Reprogram Data Computation Table Result of Verify-Read after Write Pulse Application (V) Result of Operation Comments Programming completed: reprogramming processing not to be executed Programming incomplete: reprogramming processing to be executed  Still in erased state: no action Legend (D): Source data of bits on which programming is executed (X): Source data of bits on which reprogramming is executed Additional-Programming Data Computation Table Result of Verify-Read...
Page 568 Start of programming Write pulse application subroutine Perform programming in the erased state. Sub-Routine Write Pulse START Do not perform additional programming on previously programmed addresses. Set SWE bit in FLMCR1 WDT enable ) µs Wait (t sswe Set PSU bit in FLMCR1 Store 128-byte program data in program ) µs data area and reprogram data area...
Page 569: Erase Mode
18.6.3 Erase Mode When erasing flash memory, the single-block erase flowchart shown in figure 18.11 should be followed. The wait times after bits are set or cleared in the flash memory control register 1 (FLMCR1) and the maximum number of erase operations (N) are shown in table 22.30 in section 22.3.6, Flash Memory Characteristics.
Page 570 Start Perform erasing in block units. Set SWE bit in FLMCR1 ) µs Wait (t sswe n = 1 Set EBR1 or EBR2 *3, *4 Enable WDT Set ESU bit in FLMCR1 ) µs Wait (t sesu Start of erase Set E bit in FLMCR1 Wait (t ) ms...
Page 571: Flash Memory Protection
18.7 Flash Memory Protection There are three kinds of flash memory program/erase protection: hardware, software, and error protection. 18.7.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. In this state, the settings in flash memory control register 1 (FLMCR1) and erase block registers 1 and 2 (EBR1, EBR2) are reset.
Page 572: Software Protection
3. All blocks are unerasable and block-by-block specification is not possible. 4. See section 4.2.2, Reset Sequence, and section 18.11, Flash Memory Programming and Erasing Precautions. The H8/3064F-ZTAT requires a minimum of 20 system clock cycles for a reset during operation. 18.7.2 Software Protection Software protection can be implemented by setting the erase block register 1 (EBR1), erase block...
Page 573 setting the P or E bit in FLMCR. However, PV and EV bit setting is enabled, and a transition can be made to verify mode* FLER bit setting conditions are as follows: 1. When flash memory is read during programming/erasing (including a vector read or instruction fetch) 2.
Page 574 Reset or standby Program mode (hardware protection) Erase mode RES = 0 or STBY = 0 RD VF PR ER FLER = 0 RD VF PR ER INIT FLER = 0 RES = 0 or Error occurrence STBY = 0 FLMCR1, FLMCR2, (software standby) EBR1, EBR2...
Page 575 18.8 Flash Memory Emulation in RAM Making a setting in the RAM control register (RAMCR) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time.
Page 576 This area can be accessed from both the RAM area and flash memory area H'00000 H'01000 H'02000 H'03000 H'04000 H'05000 H'06000 H'07000 H'08000 H'FFE000 H'FFEFFF Flash memory EB8 to EB11 On-chip RAM H'FFFF1F H'3FFFF Figure 18.14 Example of RAM Overlap Operation Example of Flash Memory Block Area EB0 Overlapping 1.
Page 577: Nmi Input Disabling Conditions
4. As in on-board programming mode, care is required when applying and releasing FWE to prevent erroneous programming or erasing. To prevent erroneous programming and erasing due to program runaway during FWE application, in particular, the watchdog timer should be set when the PSU, P, ESU, or E bit is set to 1 in FLMCR1, even while the emulation function is being used.
Page 578: Flash Memory Prom Mode
The H8/3064F-ZTAT has a PROM mode as well as the on-board programming modes for programming and erasing flash memory. In PROM mode, the on-chip ROM can be freely programmed using a general-purpose PROM writer that supports the Hitachi microcomputer device type with 256-kbyte on-chip flash memory.
Page 579: 18.10.2 Notes On Use Of Prom Mode
3. The memory is initially in the erased state when the device is shipped by Hitachi. For samples for which the erasure history is unknown, it is recommended that erasing be executed to check and correct the initialization (erase) level.
Page 580 • Apply FWE when the V voltage has stabilized within its rated voltage range. If FWE is applied when the MCU’s V power supply is not within its rated voltage range, MCU operation will be unstable and flash memory may be erroneously programmed or erased.
Page 581 Also note that access to the flash memory space by means of a MOV instruction, etc., is not permitted while the P bit or E bit is set. 6. Do not set or clear the SWE bit during execution of a program in flash memory. Clear the SWE bit before executing a program or reading data in flash memory.
Page 582 Program- ming/ erasing Wait time: Wait time: possible φ Min 0 µs OSC1 Min 0 µs to MD SWE set SWE cleared SWE bit Period during which flash memory access is prohibited (x: Wait time after setting SWE bit, y: Wait time after clearing SWE bit)* Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited)
Page 583 Program- ming/ erasing Wait time: Wait time: possible φ Min 0 µs OSC1 to MD SWE set SWE cleared SWE bit Period during which flash memory access is prohibited (x: Wait time after setting SWE bit, y: Wait time after clearing SWE bit)* Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited)
Page 584 φ OSC1 Min 0µs to MD RESW SWE set cleared SWE bit Boot Mode Mode User User User program mode User program mode change change mode mode mode Period during which flash memory access is prohibited (x: Wait time after setting SWE bit, y: Wait time after clearing SWE bit)* Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1.
Page 585 Section 19 Flash Memory [H8/3062F-ZTAT A-Mask Version] 19.1 Overview The H8/3062F-ZTAT A-mask version has 128 kbytes of on-chip flash memory. The flash memory is connected to the CPU by a 16-bit data bus. The CPU accesses both byte data and word data in two states, enabling rapid data transfer.
Page 586 H'FFF400 to H'FFFF1F (2.8 kbytes) H'FFF520 to H'FFFF1F (2.5 kbytes) Programming control program identification function PROM mode Use of PROM writer supporting Hitachi Use of PROM writer supporting Hitachi microcomputer device type with 128 microcomputer device type with 128 kbytes on-chip flash memory kbytes on-chip flash memory Notes: 1.
Page 587 19.2 Features The H8/3062F-ZTAT A-mask version has 128 kbytes of on-chip flash memory. The features of the flash memory are summarized below. • Four flash memory operating modes  Program mode  Erase mode  Program-verify mode  Erase-verify mode •...
Page 588: Block Diagram
19.2.1 Block Diagram Internal address bus Internal data bus (16 bits) FLMCR1 FLMCR2 Operating FWE pin Bus interface/controller mode Mode pins RAMCR Flash memory (128 kbytes) Legend FLMCR1: Flash memory control register 1 FLMCR2: Flash memory control register 2 EBR: Erase block register RAMCR: RAM control register Figure 19.1 Block Diagram of Flash Memory...
Page 589: Pin Configuration
19.2.2 Pin Configuration The flash memory is controlled by means of the pins shown in table 19.3. Table 19.3 Flash Memory Pins Pin Name Abbreviation Function Reset Input Reset Flash write enable Input Flash program/erase protection by hardware Mode 2 Input Sets H8/3062F-ZTAT A-mask version operating mode...
Page 590 19.3 Register Descriptions 19.3.1 Flash Memory Control Register 1 (FLMCR1) Initial value —* Read/Write Note: * Determined by the state of the FWE pin. FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode for addresses H'00000 to H'1FFFF is entered by setting the SWE bit when FWE = 1, then setting the PV or EV bit.
Page 591 Bit 6—Software Write Enable (SWE): Enables or disables flash memory programming and erasing. (This bit should be set when setting bits 5 to 0 and EBR bits 7 to 0.) Bit 6 Description Programming/erasing disabled (Initial value) Programming/erasing enabled [Setting condition] When FWE = 1 Note: Do not execute a SLEEP instruction while the SWE bit is set to 1.
Page 592 Bit 2—Program-Verify Mode (PV): Selects program-verify mode transition or clearing. (Do not set the SWE, ESU, PSU, EV, E, or P bit at the same time.) Bit 2 Description Program-verify mode cleared (Initial value) Transition to program-verify mode [Setting condition] When FWE = 1 and SWE = 1 Bit 1—Erase Mode (E): Selects erase mode transition or clearing.
Page 593: Flash Memory Control Register 2 (Flmcr2)
19.3.2 Flash Memory Control Register 2 (FLMCR2) FLER — — — — — — — Initial value Read/Write FLMCR2 is an 8-bit register used for flash memory operating mode control. FLMCR2 is initialized to H'00 by a reset, and in hardware standby mode and software standby mode. When the on-chip flash memory is disabled, a read will return H'00.
Page 594 19.3.3 Erase Block Register (EBR) EBR is an 8-bit register that designates the flash memory block for erasure. EBR is initialized to H'00 by a reset, in hardware standby mode or software standby mode, when a high level is not input to the FWE pin, or when the SWE bit in FLMCR1 is 0 when a high level is applied to the FWE pin.
Page 595: Ram Control Register (Ramcr)
Table 19.5 Flash Memory Erase Blocks Block (Size) Address EB0 (1 kbyte) H'000000–H'0003FF EB1 (1 kbyte) H'000400–H'0007FF EB2 (1 kbyte) H'000800–H'000BFF EB3 (1 kbyte) H'000C00–H'000FFF EB4 (28 kbytes) H'001000–H'007FFF EB5 (32 kbytes) H'008000–H'00FFFF EB6 (32 kbytes) H'010000–H'017FFF EB7 (32 kbytes) H'018000–H'01FFFF 19.3.4 RAM Control Register (RAMCR)
Page 596 When 1 is written to the RAMS bit, all flash memory blocks are protected from programming and erasing. Bits 2 and 1—RAM2 and RAM1: These bits are used with bit 3 to reassign an area to RAM (see table 19.6). The initial setting for this bit is 0 in modes 5, 6, and 7 (internal flash memory enabled) and programming is enabled.* In modes other than 5 to 7, 0 is always read and writing is disabled.
Page 597: Overview Of Operation
19.4 Overview of Operation 19.4.1 Mode Transitions When the mode pins and the FWE pin are set in the reset state and a reset-start is executed, the H8/3062F-ZTAT A-mask version enters one of the operating modes shown in figure 19.3. In user mode, flash memory can be read but not programmed or erased.
Page 598 Reset state RES = 0 User mode with on-chip ROM RES = 0 enabled RES = 0 RES = 0 FWE = 0 PROM mode User program mode Boot mode On-board programming mode Notes: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory.
Page 599: On-Board Programming Modes
19.4.2 On-Board Programming Modes Example of Boot Mode Operation 1. Initial state 2. Programming control program transfer The old program version or data remains When boot mode is entered, the boot program written in the flash memory. The user should in the H8/3062F-ZTAT A-mask version prepare the programming control program and (originally incorporated in the chip) is started...
Page 600 Example of User Program Mode Operation 1. Initial state 2. Programming/erase control program transfer The FWE assessment program that confirms When user program mode is entered, user that user program mode has been entered, and software recognizes this fact, executes the the program that will transfer the programming/ transfer program in the flash memory, and erase control program from flash memory to...
Page 601: Flash Memory Emulation In Ram
19.4.3 Flash Memory Emulation in RAM In the H8/3062F-ZTAT A-mask version, flash memory programming can be emulated in real time by overlapping the flash memory with part of RAM (“overlap RAM”). When the emulation block set in RAMCR is accessed while the emulation function is being executed, data written in the overlap RAM is read.
Page 602: Block Configuration
Flash memory Program data Overlap RAM Application program (program data) Programming control program Execution state Figure 19.5 Writing Overlap RAM Data in User Program Mode 19.4.4 Block Configuration The flash memory in the H8/3062F-ZTAT A-mask version is divided into three 32-kbyte blocks, one 28-kbyte block, and four 1-kbyte blocks.
Page 603: On-Board Programming Mode
19.5 On-Board Programming Mode When pins are set to on-board programming mode and a reset-start is executed, the chip enters the on-board programming state in which on-chip flash memory programming, erasing, and verifying can be carried out. There are two operating modes in this mode—boot mode and user program mode.
Page 604: Boot Mode
19.5.1 Boot Mode When boot mode is used, a flash memory programming control program must be prepared beforehand in the host, and SCI channel 1, which is to be used, must be set to asynchronous mode. When a reset-start is executed after setting the H8/3062F-ZTAT A-mask version’ pins to boot mode, the boot program already incorporated in the MCU is activated, and the programming control program prepared beforehand in the host is transmitted sequentially to the H8/3062F- ZTAT A-mask version, using the SCI.
Page 605 Start Set pins to boot program mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate H8/3062F-ZTAT A-mask version measures low period of H'00 data transmitted by host H8/3062F-ZTAT A-mask version calculates bit rate and sets value in bit rate register After bit rate adjustment, H8/3062F-ZTAT A-mask version transmits one H'00 data byte to host to indicate end of adjustment...
Page 606 Automatic SCI Bit Rate Adjustment: Start Stop Low period (9 bits) measured (H'00 data) High period (1 or more bits) When boot mode is initiated, the H8/3062F-ZTAT A-mask version measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as 8-bit data, 1 stop bit, no parity.
Page 607 rate and system clock frequency within one of the ranges shown in table 19.8 can be used for boot mode execution. On-Chip RAM Area Divisions in Boot Mode: In boot mode, the RAM area is divided into an area used by the boot program and an area to which the user program is transferred via the SCI, as shown in figure 19.8.
Page 608 Notes on Use of Boot Mode: 1. When the H8/3062F-ZTAT A-mask version chip comes out of reset in boot mode, it measures the low period of the input at the SCI’s RxD pin. The reset should end with RxD high. After the reset ends, it takes about 100 states for the chip to get ready to measure the low period of the RxD input.
Page 609: User Program Mode
H8/3062F-ZTAT A-mask version External memory, etc. System control unit Notes: 1. Mode pin and FWE pin input must satisfy the mode programming setup time (t with respect to the reset release timing. 2. See section 4.2.2, Reset Sequence, and section 19.11, Flash Memory Programming and Erasing Precautions.
Page 610 Write FWE assessment program and transfer program (and programming/erase control program if necessary) beforehand –MD = 101 or 111 Reset-start Transfer programming/erase control program to RAM Branch to programming/erase control program in RAM area FWE = high (user program mode) Execute programming/erase control program in RAM (flash memory rewriting)
Page 611: Flash Memory Programming/Erasing
19.6 Flash Memory Programming/Erasing A software method, using the CPU, is employed to program and erase flash memory in the on- board programming modes. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes for addresses H'000000 to H'01FFFF are made by setting the PSU, ESU, P, E, PV, and EV bits in FLMCR1.
Page 612 E = 1 Erase setup Erase mode state E = 0 ESU = 1 Normal mode ESU = 0 FWE = 1 FWE = 0 Erase-verify EV = 1 mode On-board SWE = 1 EV = 0 Software programming mode programming Software programming enable...
Page 613: Program Mode
19.6.1 Program Mode When writing data or programs to flash memory, the program/program-verify flowchart shown in figure 19.11 should be followed. Performing programming operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability.
Page 614: Program-Verify Mode
19.6.2 Program-Verify Mode In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. After the elapse of the given programming time, clear the P bit in FLMCR1, then wait for at least ) µs before clearing the PSU bit to exit program mode.
Page 615 the number of loops in reprogramming processing is guaranteed not to exceed the maximum value of the maximum programming count (N). b. After write pulse application, a verify-read is performed in program-verify mode, and programming is judged to have been completed for bits read as 0. The following processing is necessary for programmed bits.
Page 616 Reprogram Data Computation Table Result of Verify-Read after Write Pulse Application (V) Result of Operation Comments Programming completed: reprogramming processing not to be executed Programming incomplete: reprogramming processing to be executed  Still in erased state: no action Legend (D): Source data of bits on which programming is executed (X): Source data of bits on which reprogramming is executed Additional-Programming Data Computation Table Result of Verify-Read...
Page 617 Start of programming Write pulse application subroutine Perform programming in the erased state. Sub-Routine Write Pulse START Do not perform additional programming on previously programmed addresses. Set SWE bit in FLMCR1 WDT enable ) µs Wait (t sswe Set PSU in FLMCR1 Store 128-byte program data in program ) µs data area and reprogram data area...
Page 618: Erase Mode
19.6.3 Erase Mode When erasing flash memory, the single-block erase flowchart shown in figure 19.12 should be followed. The wait times after bits are set or cleared in the flash memory control register 1 (FLMCR1) and the maximum number of erase operations (N) are shown in table 22.40 in section 22.4.6, Flash Memory Characteristics.
Page 619 Start Perform erasing in block units. Set SWE bit in FLMCR1 ) µs Wait (t sswe n = 1 Set EBR *3, *4 Enable WDT Set ESU bit in FLMCR1 ) µs Wait (t sesu Start of erase Set E bit in FLMCR1 Wait (t ) ms Clear E bit in FLMCR1...
Page 620: Flash Memory Protection
19.7 Flash Memory Protection There are three kinds of flash memory program/erase protection: hardware, software, and error protection. 19.7.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. In this state, the settings in flash memory control register 1 (FLMCR1) and erase block register (EBR) are reset.
Page 621: Software Protection
3. All blocks are unerasable and block-by-block specification is not possible. 4. See section 4.2.2, Reset Sequence, and section 19.11, Flash Memory Programming and Erasing Precautions. The H8/3062F-ZTAT A-mask version requires a minimum of 20 system clock cycles for a reset during operation. 19.7.2 Software Protection Software protection can be implemented by setting the erase block register (EBR) and the RAMS...
Page 622 FLER bit setting conditions are as follows: 1. When flash memory is read during programming/erasing (including a vector read or instruction fetch) 2. Immediately after the start of exception handling during programming/erasing (excluding reset, illegal instruction, trap instruction, and division-by-zero exception handling) 3.
Page 623 Reset or standby Program mode (hardware protection) Erase mode RES = 0 or STBY = 0 RD VF PR ER FLER = 0 RD VF PR ER INIT FLER = 0 RES = 0 or Error occurrence STBY = 0 FLMCR1, FLMCR2, (software standby) EBR1, EBR2...
Page 624 19.8 Flash Memory Emulation in RAM As flash memory programming and erasing takes time, it may be difficult to carry out tuning by writing parameters and other data in real time. In this case, real-time programming of flash memory can be emulated by overlapping part of RAM (H'FFF000–H'FFF3FF) onto a small block area in flash memory.
Page 625 Notes on Use of Emulation in RAM: 1. Flash write enable (FWE) application and releasing As in on-board program mode, care is required when applying and releasing FWE to prevent erroneous programming or erasing. To prevent erroneous programming and erasing due to program runaway during FWE application, in particular, the watchdog timer should be set when the PSU, P, ESU, or E bit is set to 1 in FLMCR1, even while the emulation function is being used.
Page 626 The H8/3062F-ZTAT A-mask version has a PROM mode as well as the on-board programming modes for programming and erasing flash memory. In PROM mode, the on-chip ROM can be freely programmed using a general-purpose PROM writer that supports the Hitachi microcomputer device type with 128-kbyte on-chip flash memory.
Page 627 3. The memory is initially in the erased state when the device is shipped by Hitachi. For samples for which the erasure history is unknown, it is recommended that erasing be executed to check and correct the initialization (erase) level.
Page 628: Flash Memory Programming And Erasing Precautions
1. Use the specified voltages and timing for programming and erasing. Applied voltages in excess of the rating can permanently damage the device. Use a PROM programmer that supports the Hitachi microcomputer device type with 128-kbyte on-chip flash memory. 2. Powering on and off (see figures 19.16 to 19.18) Do not apply a high level to the FWE pin until V has stabilized.
Page 629 • In user program mode, FWE can be switched between high and low level regardless of RES input. FWE input can also be switched during execution of a program in flash memory. • Do not apply FWE if program runaway has occurred. During FWE application, the program execution state must be monitored using the watchdog timer or some other means.
Page 630 8. Do not perform additional programming. Erase the memory before reprogramming. In on-board programming, perform only one programming operation on a 128-byte programming unit block. Programming should be carried out with the entire programming unit block erased. 9. Before programming, check that the chip is correctly mounted in the PROM writer. Overcurrent damage to the device can result if the index marks on the PROM writer socket, socket adapter, and chip are not correctly aligned.
Page 631 Program- ming/ erasing Wait time: Wait time: possible φ Min 0 µs OSC1 Min 0 µs to MD SWE set SWE cleared SWE bit Period during which flash memory access is prohibited (x: Wait time after setting SWE bit, y: Wait time after clearing SWE bit)* Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited)
Page 632 Program- ming/ erasing Wait time: Wait time: possible φ Min 0 µs OSC1 to MD SWE set SWE cleared SWE bit Period during which flash memory access is prohibited (x: Wait time after setting SWE bit, y: Wait time after clearing SWE bit)* Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited)
Page 633 φ OSC1 Min 0µs to MD RESW SWE set cleared SWE bit Boot Mode Mode User User User program mode User program mode change change mode mode mode Period during which flash memory access is prohibited (x: Wait time after setting SWE bit, y: Wait time after clearing SWE bit)* Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1.
Page 634: Notes When Converting The F-Ztat Application Software To The Mask-Rom Versions
19.12 Notes when Converting the F-ZTAT Application Software to the Mask-ROM Versions Please note the following when converting the F-ZTAT application software to the mask-ROM versions. The values read from the internal registers for the flash ROM or the mask-ROM version and F- ZTAT version differ as follows.
Page 635: Section 20 Clock Pulse Generator
20.1 Overview The H8/3062 Series has a built-in clock pulse generator (CPG) that generates the system clock (φ) and other internal clock signals (φ/2 to φ/4096). After duty adjustment, a frequency divider divides the clock frequency to generate the system clock (φ). The system clock is output at the φ pin* furnished as a master clock to prescalers that supply clock signals to the on-chip supporting modules.
Page 636: Oscillator Circuit
20.2 Oscillator Circuit Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock signal. 20.2.1 Connecting a Crystal Resonator Circuit Configuration: A crystal resonator can be connected as in the example in figure 20.2. Damping resistance Rd should be selected according to table 20.1 (1), and external capacitances and C according to table 20.1 (2).
Page 637 When the board is designed, the crystal resonator and its load capacitors should be placed as close as possible to the XTAL and EXTAL pins. Avoid Signal A Signal B H8/3062 Series XTAL EXTAL Figure 20.4 Oscillator Circuit Block Board Design Precautions...
Page 638: External Clock Input
20.2.2 External Clock Input Circuit Configuration: An external clock signal can be input as shown in the examples in figure 20.5. If the XTAL pin is left open, the stray capacitance should not exceed 10 pF. If the stray capacitance at the XTAL pin exceeds 10 pF in configuration a, use the connection shown in configuration b instead, and hold the external clock high in standby mode.
Page 639 Table 20.3 (1) Clock Timing for On-Chip Flash Memory Versions = 3.0 V = 5.0 V to 5.5 V ± 10% Item Symbol Min Unit Test Conditions External clock input low — — Figure 20.6 pulse width External clock input high —...
Page 640: Duty Adjustment Circuit
× 0.7 EXTAL × 0.5 0.3 V Figure 20.6 External Clock Input Timing STBY EXTAL φ (internal or external) DEXT Figure 20.7 External Clock Output Settling Delay Timing 20.3 Duty Adjustment Circuit When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate φ.
Page 641: Register Configuration
frequency division ratio. The system clock generated by the frequency divider can be output at the φ pin. 20.5.1 Register Configuration Table 20.4 summarizes the frequency division register. Table 20.4 Frequency Division Register Address* Name Abbreviation Initial Value H'EE01B Division control register DIVCR H'FC Note: * Lower 20 bits of the address in advanced mode.
Page 642: Usage Notes
= lower limit of the operating frequency range. Ensure that ø is not below this lower limit. Table 20.5 shows the operating frequency ranges of the various models in the H8/3062 Series. Table 20.5 Comparison of H8/3062 Series Operating Frequency Ranges...
Page 643: Section 21 Power-Down State
Section 21 Power-Down State 21.1 Overview The H8/3062 Series has a power-down state that greatly reduces power consumption by halting the CPU, and a module standby function that reduces power consumption by selectively halting on-chip modules. The power-down state includes the following three modes: •...
Page 644 Table 21.1 Power-Down State and Module Standby Function...
Page 645: Register Configuration
21.2 Register Configuration The H8/3062 Series has a system control register (SYSCR) that controls the power-down state, and module standby control registers H (MSTCRH) and L (MSTCRL) that control the module standby function. Table 21.2 summarizes these registers. Table 21.2 Control Register...
Page 646 7 ms. See table 21.3. If an external clock is used, the choice of settings depends on the H8/3062 Series version. 1. H8/3062F-ZTAT, H8/3062F-ZTAT R-mask version, H8/3062 mask ROM version, H8/3061 mask ROM version, H8/3060 mask ROM version: Any setting is permitted.
Page 647: Module Standby Control Register H (Mstcrh)
Bit 1—Software Standby Output Port Enable (SSOE): Specifies whether the address bus and to CS , AS, RD, HWR, and LWR) are kept as outputs or fixed high, or bus control signals (CS placed in the high-impedance state in software standby mode. Bit 1 SSOE Description...
Page 648: Module Standby Control Register L (Mstcrl)
Bits 6 to 3—Reserved: These bits cannot be modified and are always read as 1. Bit 2—Reserved: This bit can be written and read. Bit 1—Module Standby H1 (MSTPH1): Selects whether to place the SCI1 in standby. Bit 1 MSTPH1 Description SCI1 operates normally (Initial value)
Page 649 Bits 7 to 5—Reserved: This bit can be written and read. Bit 4—Module Standby L4 (MSTPL4): Selects whether to place the 16-bit timer in standby. Bit 4 MSTPL4 Description 16-bit timer operates normally (Initial value) 16-bit timer is in standby state Bit 3—Module Standby L3 (MSTPL3): Selects whether to place 8-bit timer channels 0 and 1 in standby.
Page 650: Sleep Mode
21.3 Sleep Mode 21.3.1 Transition to Sleep Mode When the SSBY bit is cleared to 0 in SYSCR, execution of the SLEEP instruction causes a transition from the program execution state to sleep mode. Immediately after executing the SLEEP instruction the CPU halts, but the contents of its internal registers are retained. On-chip supporting modules do not halt in sleep mode.
Page 651: Exit From Software Standby Mode
7 ms. Table 21.3 indicates the waiting times that are selected by STS2 to STS0, DIV1, and DIV0 settings at various system clock frequencies. When Using an External Clock 1. H8/3062F-ZTAT, H8/3062F-ZTAT R-mask version, H8/3062 mask ROM version, H8/3061 mask ROM version, H8/3060 mask ROM version: Any setting is permitted.
Page 652 Table 21.3 Clock Frequency and Waiting Time for Clock to Settle DIV1 DIV0 STS2 STS1 STS0 Waiting Time 25 MHz 20 MHz 18 MHz 16 MHz 12 MHz 10 MHz 8 MHz 6 MHz 4 MHz 2 MHz 1MHz Unit 8.2* 8192 states 0.46...
Page 653: Sample Application Of Software Standby Mode
21.4.4 Sample Application of Software Standby Mode Figure 21.1 shows an example in which software standby mode is entered at the fall of NMI and exited at the rise of NMI. With the NMI edge select bit (NMIEG) cleared to 0 in SYSCR (selecting the falling edge), an NMI interrupt occurs.
Page 654: Cautions On Clearing The Software Standby Mode Of F-Ztat Version
• Addresses H'E000 to H'E0FF (internal I/O registers-1): H'yyyy → H'Eyyyy • Addresses H'EF20 and above (on-chip RAM area and internal I/O registers-2): H'zzzz → H'Fzzzz (Where x, y and z are any hexadecimal numbers) (3) Comparison of products in H8/3062 Series H8/3062F-ZTAT H8/3062F-ZTAT H8/3062F-ZTAT R-Mask Version...
Page 655: Hardware Standby Mode
21.5 Hardware Standby Mode 21.5.1 Transition to Hardware Standby Mode Regardless of its current state, the chip enters hardware standby mode whenever the STBY pin goes low. Hardware standby mode reduces power consumption drastically by halting all functions of the CPU, and on-chip supporting modules. All modules are reset except the on-chip RAM. As long as the specified voltage is supplied, on-chip RAM data is retained.
Page 656: Module Standby Function
21.6 Module Standby Function 21.6.1 Module Standby Timing The module standby function can halt several of the on-chip supporting modules (SCI1, SCI0, 16- bit timer, 8-bit timer, and A/D converter) independently in the power-down state. This standby function is controlled by bits MSTPH2 to MSTPH0 in MSTCRH and bits MSTPL7 to MSTPL0 in MSTCRL.
Page 657: System Clock Output Disabling Function
21.7 System Clock Output Disabling Function Output of the system clock (φ) can be controlled by the PSTOP bit in MSTCRH. When the PSTOP bit is set to 1, output of the system clock halts and the φ pin is placed in the high- impedance state.
Page 658: Section 22 Electrical Characteristics
Section 22 Electrical Characteristics Table 22.1 shows the electrical characteristics of the various products in the H8/3062 Series. Table 22.1 Electrical Characteristics of H8/3062 Series Products H8/3062 H8/3062 F-ZTAT H8/3062 F-ZTAT H8/3062 R-Mask H8/3061 H8/3064 A-Mask Item Symbol Unit F-ZTAT...
Page 659 H8/3062 H8/3062 F-ZTAT H8/3062 F-ZTAT H8/3062 R-Mask H8/3061 H8/3064 A-Mask Item Symbol Unit F-ZTAT Version H8/3060 F-ZTAT Version AC charac- Clock cycle Max 1000 Max 1000 Max 1000 Max 500 Max 500 teristics time RES pulse Min 20 Min 20...
Page 660: Electrical Characteristics Of H8/3062 Mask Rom Version, H8/3061 Mask Rom Version, And H8/3060 Mask Rom Version
22.1 Electrical Characteristics of H8/3062 Mask ROM Version, H8/3061 Mask ROM Version, and H8/3060 Mask ROM Version 22.1.1 Absolute Maximum Ratings Table 22.2 lists the absolute maximum ratings. Table 22.2 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage –0.3 to +7.0...
Page 661: Dc Characteristics
22.1.2 DC Characteristics Table 22.3 lists the DC characteristics. Table 22.4 lists the permissible output currents. Table 22.3 DC Characteristics (1) Conditions: V = 5.0 V ± 10%, AV = 5.0 V ± 10%, V = 4.5 V to AV = AV = 0 V* = –20°C to +75°C (regular specifications),...
Page 662 Item Symbol Unit Test Conditions Three-state Ports 1 to 6 — — µA = 0.5 V to leakage Ports 8 to B – 0.5 V current RESO — — 10.0 µA = 0 V Input pull-up Ports 2, 4, –I —...
Page 663 max. (under normal operations) = 1.0 (mA) + 0.90 (mA/(MHz × V)) × V × f 3. I = 1.0 (mA) + 0.65 (mA/(MHz × V)) × V × f max. (when using the sleeve) max. (when the sleeve + module are standing by) = 1.0 (mA) + 0.45 (mA/(MHz ×...
Page 664 Table 22.3 DC Characteristics (2) Conditions: V = 2.7 to 5.5 V, AV = 2.7 to 5.5 V, V = 2.7 V to AV = AV = 0 V* = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item Symbol Unit...
Page 665 Item Symbol Unit Test Conditions Three-state Ports 1 to 6 — — µA = 0.5 V to leakage Ports 8 to B – 0.5 V current RESO — — 10.0 µA = 0 V Input pull-up Ports 2, 4, –I —...
Page 666 max. (under normal operations) = 1.0 (mA) + 0.90 (mA/(MHz × V)) × V × f 3. I = 1.0 (mA) + 0.65 (mA/(MHz × V)) × V × f max. (when using the sleeve) max. (when the sleeve + module are standing by) = 1.0 (mA) + 0.45 (mA/(MHz ×...
Page 667 Table 22.3 DC Characteristics (3) Conditions: V = 3.0 to 5.5 V, AV = 3.0 to 5.5 V, V = 3.0 V to AV = AV = 0 V* = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item Symbol Unit...
Page 668 Item Symbol Unit Test Conditions Three-state Ports 1 to 6 — — µA = 0.5 V to leakage Ports 8 to B – 0.5 V current RESO — — 10.0 µA = 0 V Input pull-up Ports 2, 4, –I —...
Page 669 max. (under normal operations) = 1.0 (mA) + 0.90 (mA/(MHz × V)) × V × f 3. I = 1.0 (mA) + 0.65 (mA/(MHz × V)) × V max. (when using the sleeve) max. (when the sleeve + module are standing by) = 1.0 (mA) + 0.45 (mA/(MHz ×...
Page 670 Notes: 1. To protect chip reliability, do not exceed the output current values in table 22.4. 2. When directly driving a darlington pair or LED, always insert a current-limiting resistor in the output line, as shown in figures 22.1 and 22.2. H8/3062 mask ROM version H8/3061 mask ROM version H8/3060 mask ROM version 2 kΩ...
Page 671 H8/3062 mask ROM version H8/3061 mask ROM version H8/3060 mask ROM version 600 Ω Ports 1, 2, 5 Figure 22.2 Sample LED Circuit...
Page 672: Ac Characteristics
22.1.3 AC Characteristics Clock timing parameters are listed in table 22.5, control signal timing parameters in table 22.6, and bus timing parameters in table 22.7. Timing parameters of the on-chip supporting modules are listed in table 22.8. Table 22.5 Clock Timing Condition: = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range...
Page 673 Table 22.6 Control Signal Timing Condition: = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Condition A: V = 2.7 to 5.5 V, AV = 2.7 to 5.5 V, V = 2.7 to AV = AV = 0 V Condition B: V = 3.0 to 5.5 V, AV...
Page 674 Table 22.7 Bus Timing Condition: = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Condition A: V = 2.7 to 5.5 V, AV = 2.7 to 5.5 V, V = 2.7 to AV = AV = 0 V Condition B: V = 3.0 to 5.5 V, AV = 3.0 to 5.5 V, V...
Page 675 Condition Test Item Symbol Unit Conditions Write data delay — — — Figure 22.17, time figure 22.18 Write data setup 1.0 t — 1.0 t — 1.0 t — WDS1 time 1 – 50 – 40 – 30 Write data setup 2.0 t —...
Page 676 Table 22.8 Timing of On-Chip Supporting Modules Condition: = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Condition A: V = 2.7 to 5.5 V, AV = 2.7 to 5.5 V, V = 2.7 to AV = AV = 0 V Condition B: V...
Page 677 Condition Test Module Item Symbol Min Unit Conditions Input Asyn- — — — Figure 22.24 Scyc clock chronous cycle Syn- — — — chronous Input clock rise — — — SCKr time Input clock fall — — — SCKf time Input clock SCKW Scyc...
Page 678: A/D Conversion Characteristics
22.1.4 A/D Conversion Characteristics Table 22.9 lists the A/D conversion characteristics. Table 22.9 A/D Conversion Characteristics Condition: = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Condition A: V = 2.7 to 5.5 V, AV = 2.7 to 5.5 V, V = 2.7 to AV = AV = 0 V,...
Page 679 Condition Item Min Typ Max Min Typ Max Min Typ Max Unit Conver- Resolution bits sion time: Conversion time (single — — — — — — 70 states mode) Analog input capacitance — — — — — — φ ≤ 13 MHz Permissible —...
Page 680: D/A Conversion Characteristics
22.1.5 D/A Conversion Characteristics Table 22.10 lists the D/A conversion characteristics. Table 22.10 D/A Conversion Characteristics Condition: = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Condition A: V = 2.7 to 5.5 V, AV = 2.7 to 5.5 V, V = 2.7 to AV = AV = 0 V,...
Page 681: Electrical Characteristics Of H8/3062F-Ztat And H8/3062F-Ztat R-Mask Version
22.2 Electrical Characteristics of H8/3062F-ZTAT and H8/3062F-ZTAT R-Mask Version 22.2.1 Absolute Maximum Ratings Table 22.11 lists the absolute maximum ratings. Table 22.11 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage –0.3 to +7.0 Input voltage (FWE)* –0.3 to V +0.3 Input voltage (except for port 7)* –0.3 to V...
Page 682: Dc Characteristics
22.2.2 DC Characteristics Tables 22.12 lists the DC characteristics. Table 22.13 lists the permissible output currents. Table 22.12 DC Characteristics (1) Conditions: V = 5.0 V ± 10%, AV = 5.0 V ± 10%, V = 4.5 V to AV = AV = 0 V* = –20°C to +75°C (regular specifications),...
Page 683 Item Symbol Unit Test Conditions Three-state Ports 1 to 6 — — µA = 0.5 V to leakage Ports 8 to B – 0.5 V current Input pull-up Ports 2, 4, –I — µA = 0 V MOS current and 5 Input —...
Page 684 max. (normal operation)= 1.0 (mA) + 0.90 (mA/(MHz × V)) × V × f 3. I = 1.0 (mA) + 0.65 (mA/(MHz × V)) × V × f max. (sleep mode) max. (sleep mode + module standby mode) = 1.0 (mA) + 0.45 (mA/(MHz × V)) × V ×...
Page 685 Table 22.12 DC Characteristics (2) Conditions: V = 3.0 to 5.5 V, AV = 3.0 to 5.5 V, V = 3.0 V to AV = AV = 0 V* = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) [Programming/erasing conditions: V = 3.0 to 3.6 V, T = 0 to +75°C...
Page 686 Item Symbol Unit Test Conditions Three-state Ports 1 to 6 — — µA = 0.5 V to leakage Ports 8 to B – 0.5 V current Input pull-up Ports 2, 4, –I — µA = 0 V MOS current and 5 Input —...
Page 687 max. (normal operation)= 1.0 (mA) + 0.90 (mA/(MHz × V)) × V × f 3. I = 1.0 (mA) + 0.65 (mA/(MHz × V)) × V × f max. (sleep mode) max. (sleep mode + module standby mode) = 1.0 (mA) + 0.45 (mA/(MHz × V)) × V ×...
Page 688 Table 22.13 Permissible Output Currents Conditions: V = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = 3.0 V to AV = AV = 0 V, T = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item Symbol Unit...
Page 689 H8/3062F-ZTAT or H8/3062F-ZTAT R-mask version 600 Ω Ports 1, 2, 5 Figure 22.5 Sample LED Circuit...
Page 690: Ac Characteristics
22.2.3 AC Characteristics Clock timing parameters are listed in table 22.14, control signal timing parameters in table 22.15, and bus timing parameters in table 22.16. Timing parameters of the on-chip supporting modules are listed in table 22.17. Table 22.14 Clock Timing Condition: = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range...
Page 691 Table 22.15 Control Signal Timing Condition: = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Condition A: V = 3.0 to 5.5 V, AV = 3.0 to 5.5 V, V = 3.0 to AV = AV = 0 V, fmax = 13 MHz Condition B: V...
Page 692 Table 22.16 Bus Timing Condition: = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Condition A: V = 3.0 to 5.5 V, AV = 3.0 to 5.5 V, V = 3.0 to AV = AV = 0 V, fmax = 13 MHz Condition B: V = 5.0 V ±...
Page 693 Condition Test Item Symbol Unit Conditions Write data delay time — — Figure 22.17, figure 22.18 Write data setup time 1 1.0 t — 1.0 t — WDS1 – 40 – 30 Write data setup time 2 2.0 t — 2.0 t —...
Page 694 Table 22.17 Timing of On-Chip Supporting Modules Condition: = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Condition A: V = 3.0 to 5.5 V, AV = 3.0 to 5.5 V, V = 3.0 to AV = AV = 0 V, fmax = 13 MHz...
Page 695 Condition Test Module Item Symbol Unit Conditions Input clock Asyn- — — Figure 22.24 Scyc cycle chronous Syn- — — Scyc chronous Input clock rise time — — SCKr Input clock fall time — — SCKf Input clock pulse width t SCKW Scyc Transmit data delay...
Page 696: A/D Conversion Characteristics
22.2.4 A/D Conversion Characteristics Table 22.18 lists the A/D conversion characteristics. Table 22.18 A/D Conversion Characteristics Condition: = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Condition A: V = 3.0 to 5.5 V, AV = 3.0 to 5.5 V, V = 3.0 to AV = AV = 0 V,...
Page 697 Condition Item Unit Conversion time: Resolution bits 70 states Conversion time (single — — — — mode) Analog input capacitance — — — — φ ≤ 13 MHz Permissible — — — — — kΩ signal-source φ > 13 MHz —...
Page 698: D/A Conversion Characteristics
22.2.5 D/A Conversion Characteristics Table 22.19 lists the D/A conversion characteristics. Table 22.19 D/A Conversion Characteristics Condition: = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Condition A: V = 3.0 to 5.5 V, AV = 3.0 to 5.5 V, V = 3.0 to AV = AV = 0 V,...
Page 699: Flash Memory Characteristics
22.2.6 Flash Memory Characteristics Table 22.20 shows the flash memory characteristics. Table 22.20 Flash Memory Characteristics (1) Conditions: V = 4.5 to 5.5 V, AV = 4.5 to 5.5 V, V = AV = 0 V = 0 to +75°C (Programming/erasing operating temperature range: regular specification) = 0 to +85°C (Programming/erasing operating temperature range: wide-range specification)
Page 700 3. Block erase time (Shows the total period for which the E-bit in FLMCR is set. It does not include the erase verification time.) 4. To specify the maximum programming time (t (max)) in the 32-byte programming flowchart, set the maximum value (403) for the maximum programming count (N). The wait time after P bit setting (z) should be changed as follows according to the programming counter value.
Page 701 Table 22.20 Flash Memory Characteristics (2) Conditions: V = 3.0 to 3.6 V, AV = 3.0 to 3.6 V, V = AV = 0 V = 0 to +75°C (Programming/erasing operating temperature range: regular specification) = 0 to +85°C (Programming/erasing operating temperature range: wide-range specification) Item Symbol...
Page 702 4. To specify the maximum programming time (t (max)) in the 32-byte programming flowchart, set the maximum value (403) for the maximum programming count (N). The wait time after P bit setting (z) should be changed as follows according to the programming counter value.
Page 703: Electrical Characteristics Of H8/3064F-Ztat
22.3 Electrical Characteristics of H8/3064F-ZTAT 22.3.1 Absolute Maximum Ratings Table 22.21 lists the absolute maximum ratings. Table 22.21 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage 5 V operation model: -0.3 to +7.0 3 V operation model: -0.3 to +4.6 Input voltage (FWE)* –0.3 to V +0.3...
Page 704: Dc Characteristics
22.3.2 DC Characteristics Table 22.22 lists the DC characteristics. Table 22.23 lists the permissible output currents. Table 22.22 DC Characteristics (1) Conditions: V = 5.0 V ± 10%, AV = 5.0 V ± 10%, V = 4.5 V to AV = AV = 0 V, T = –20°C to +75°C...
Page 705 Item Symbol Unit Test Conditions Three-state Ports 1 to 6 — — µA = 0.5 V to leakage Ports 8 to B – 0.5 V current Input pull-up Ports 2, 4, –I — µA = 0 V MOS current and 5 Input —...
Page 706 Item Symbol Unit Test Conditions Reference During A/D — 0.45 current conversion During A/D — and D/A conversion Idle — 0.01 µA DASTE = 0 RAM standby voltage — — Notes: 1. If the A/D converter is not used, do not leave the AV , and AV pins open.
Page 707 Table 22.22 DC Characteristics (2) — Preliminary — Conditions: V = 3.0 to 3.6 V, AV = 3.0 to 3.6 V, V = 3.0 V to AV = AV = 0 V, T = –20°C to +75°C [Programming/erasing conditions: T = 0°C to +75°C] Item Symbol...
Page 708 Item Symbol Unit Test Conditions Three-state Ports 1 to 6 — — µA = 0.5 V to leakage Ports 8 to B – 0.5 V current Input pull-up Ports 2, 4, –I — µA = 0 V MOS current and 5 Input —...
Page 709 max. (normal operation)= 3.0 (mA) + 0.46 (mA/(MHz × V)) × V × f 3. I = 3.0 (mA) + 0.40 (mA/(MHz × V)) × V × f max. (sleep mode) max. (sleep mode + module standby mode) = 3.0 (mA) + 0.27 (mA/(MHz × V)) × V ×...
Page 710 Table 22.23 Permissible Output Currents Conditions: V = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = 3.0 V to AV = AV = 0 V, T = –40°C to +75°C Item Symbol Unit Permissible output Ports 1, 2, and 5 —...
Page 711 H8/3064F-ZTAT 600 Ω Ports 1, 2, 5 Figure 22.8 Sample LED Circuit...
Page 712: Ac Characteristics
22.3.3 AC Characteristics Clock timing parameters are listed in table 22.24, control signal timing parameters in table 22.25, and bus timing parameters in table 22.26. Timing parameters of the on-chip supporting modules are listed in table 22.27. Table 22.24 Clock Timing Condition: = –20°C to +75°C Condition A: V...
Page 713 Table 22.25 Control Signal Timing Condition: = –20°C to +75°C Condition A: V = 3.0 to 3.6 V, AV = 3.0 to 3.6 V, V = 3.0 to AV = AV = 0 V, fmax = TBD Condition B: V = 5.0 V ±...
Page 714 Table 22.26 Bus Timing Condition: = –20°C to +75°C Condition A: V = 3.0 to 3.6 V, AV = 3.0 to 3.6 V, V = 3.0 to AV = AV = 0 V, fmax = TBD Condition B: V = 5.0 V ± 10%, AV = 5.0 V ±...
Page 715 Condition B and C Test Item Symbol Unit Conditions Read data access — 2.0 t — 2.0 t Figure 22.17, ACC1 time 1 – 80 – 45 figure 22.18 Read data access — 3.0 t — 3.0 t ACC2 time 2 –...
Page 716 Table 22.27 Timing of On-Chip Supporting Modules Condition: = –20°C to +75°C Condition A: V = 3.0 to 3.6 V, AV = 3.0 to 3.6 V, V = 3.0 to AV = AV = 0 V, fmax = TBD Condition B: V = 5.0 V ±...
Page 717 Condition B and C Test Module Item Symbol Min Unit Conditions Input Asyn- — — Figure 22.24 Scyc clock chronous cycle Syn- — — chronous Input clock rise — — SCKr time Input clock fall time t — — SCKf Input clock SCKW Scyc...
Page 718: A/D Conversion Characteristics
22.3.4 A/D Conversion Characteristics Table 22.28 lists the A/D conversion characteristics. Table 22.28 A/D Conversion Characteristics Condition: = –20°C to +75°C Condition A: V = 3.0 to 3.6 V, AV = 3.0 to 3.6 V, V = 3.0 to AV = AV = 0 V, fmax = TBD...
Page 719 Condition B and C Item Unit Conver- Resolution bits sion time: Conversion time (single — — — — 70 states mode) Analog input capacitance — — — — φ ≤ 13 MHz Permissible — — — — — kΩ signal-source φ...
Page 720: D/A Conversion Characteristics
22.3.5 D/A Conversion Characteristics Table 22.29 lists the D/A conversion characteristics. Table 22.29 D/A Conversion Characteristics Condition: = –20°C to +75°C Condition A: V = 3.0 to 3.6 V, AV = 3.0 to 3.6 V, V = 3.0 to AV = AV = 0 V, fmax = TBD...
Page 721: Flash Memory Characteristics
22.3.6 Flash Memory Characteristics Table 22.30 shows the flash memory characteristics. Table 22.30 Flash Memory Characteristics (1) Conditions: V = 4.5 to 5.5 V, AV = 4.5 to 5.5 V, V = AV = 0 V, = 0°C to +75°C (operating temperature range for programming/erasing) Item Symbol Unit...
Page 722 Notes: 1. Make each time setting in accordance with the program/program-verify flowchart or erase/erase-verify flowchart. 2. Programming time per 128 bytes (Shows the total period for which the P-bit in the flash memory control register (FLMCR) is set. It does not include the programming verification time.) 3.
Page 723 Table 22.30 Flash Memory Characteristics (2) — Preliminary — Conditions: V = 3.0 to 3.6 V, AV = 3.0 to 3.6 V, V = AV = 0 V = 0°C to +75°C (operating temperature range for programming/erasing) Item Symbol Unit Notes Programming time* —...
Page 724 Notes: 1. Make each time setting in accordance with the program/program-verify flowchart or erase/erase-verify flowchart. 2. Programming time per 128 bytes (Shows the total period for which the P-bit in the flash memory control register (FLMCR) is set. It does not include the programming verification time.) 3.
Page 725: Electrical Characteristics Of H8/3062F-Ztat A-Mask Version
22.4 Electrical Characteristics of H8/3062F-ZTAT A-Mask Version 22.4.1 Absolute Maximum Ratings Table 22.31 lists the absolute maximum ratings. Table 22.31 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage 5 V operation model: -0.3 to +7.0 3 V operation model: -0.3 to +4.6 Input voltage (FWE)* –0.3 to V +0.3...
Page 726: Dc Characteristics
22.4.2 DC Characteristics Table 22.32 lists the DC characteristics. Table 22.33 lists the permissible output currents. Table 22.32 DC Characteristics (1) Conditions: V = 5.0 V ± 10%, AV = 5.0 V ± 10%, V = 4.5 V to AV = AV = 0 V, T = –20°C to +75°C...
Page 727 Item Symbol Unit Test Conditions Three-state Ports 1 to 6 — — µA = 0.5 V to leakage Ports 8 to B – 0.5 V current Input pull-up Ports 2, 4, –I — µA = 0 V MOS current and 5 Input —...
Page 728 Item Symbol Unit Test Conditions Reference During A/D — 0.45 current conversion During A/D — and D/A conversion Idle — 0.01 µA DASTE = 0 RAM standby voltage — — Notes: 1. If the A/D converter is not used, do not leave the AV , and AV pins open.
Page 729 Table 22.32 DC Characteristics (2) — Preliminary — Conditions: V = 3.0 to 3.6 V, AV = 3.0 to 3.6 V, V = 3.0 V to AV = AV = 0 V, T = –20°C to +75°C [Programming/erasing conditions: T = 0°C to +75°C] Item Symbol...
Page 730 Item Symbol Unit Test Conditions Three-state Ports 1 to 6 — — µA = 0.5 V to leakage Ports 8 to B – 0.5 V current Input pull-up Ports 2, 4, –I — µA = 0 V MOS current and 5 Input —...
Page 731 max. (normal operation)= 3.0 (mA) + 0.40 (mA/(MHz × V)) × V × f 3. I = 3.0 (mA) + 0.32 (mA/(MHz × V)) × V × f max. (sleep mode) max. (sleep mode + module standby mode) = 3.0 (mA) + 0.25 (mA/(MHz × V)) × V ×...
Page 732 Table 22.33 Permissible Output Currents Conditions: V = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = 3.0 V to AV = AV = 0 V, T = –40°C to +75°C Item Symbol Unit Permissible output Ports 1, 2, and 5 —...
Page 733 H8/3062F-ZTAT A-mask version 600 Ω Ports 1, 2, 5 Figure 22.11 Sample LED Circuit...
Page 734: Ac Characteristics
22.4.3 AC Characteristics Clock timing parameters are listed in table 22.34, control signal timing parameters in table 22.35, and bus timing parameters in table 22.36. Timing parameters of the on-chip supporting modules are listed in table 22.37. Table 22.34 Clock Timing Condition: = –20°C to +75°C Condition A: V...
Page 735 Table 22.35 Control Signal Timing — Preliminary — Condition: = –20°C to +75°C Condition A: V = 3.0 to 3.6 V, AV = 3.0 to 3.6 V, V = 3.0 to AV = AV = 0 V, fmax = TBD Condition B: V = 5.0 V ±...
Page 736 Table 22.36 Bus Timing Condition: = –20°C to +75°C Condition A: V = 3.0 to 3.6 V, AV = 3.0 to 3.6 V, V = 3.0 to AV = AV = 0 V, fmax = TBD Condition B: V = 5.0 V ± 10%, AV = 5.0 V ±...
Page 737 Condition B and C Test Item Symbol Unit Conditions Read data access — 2.0 t — 2.0 t Figure 22.17, ACC1 time 1 – 80 – 45 figure 22.18 Read data access — 3.0 t — 3.0 t ACC2 time 2 –...
Page 738 Table 22.37 Timing of On-Chip Supporting Modules — Preliminary — Condition: = –20°C to +75°C Condition A: V = 3.0 to 3.6 V, AV = 3.0 to 3.6 V, V = 3.0 to AV = AV = 0 V, fmax = TBD Condition B: V = 5.0 V ±...
Page 739 Condition B and C Test Module Item Symbol Min Unit Conditions Input Asyn- — — Figure 22.24 Scyc clock chronous cycle Syn- — — chronous Input clock rise — — SCKr time Input clock fall time t — — SCKf Input clock SCKW Scyc...
Page 740: A/D Conversion Characteristics
22.4.4 A/D Conversion Characteristics Table 22.38 lists the A/D conversion characteristics. Table 22.38 A/D Conversion Characteristics Condition: = –20°C to +75°C Condition A: V = 3.0 to 3.6 V, AV = 3.0 to 3.6 V, V = 3.0 to AV = AV = 0 V, fmax = TBD...
Page 741 Condition B and C Item Unit Conver- Resolution bits sion time: Conversion time (single — — — — 70 states mode) Analog input capacitance — — — — φ ≤ 13 MHz Permissible — — — — — kΩ signal-source φ...
Page 742: D/A Conversion Characteristics
22.4.5 D/A Conversion Characteristics Table 22.39 lists the D/A conversion characteristics. Table 22.39 D/A Conversion Characteristics Condition: = –20°C to +75°C Condition A: V = 3.0 to 3.6 V, AV = 3.0 to 3.6 V, V = 3.0 to AV = AV = 0 V, fmax = TBD...
Page 743: Flash Memory Characteristics
22.4.6 Flash Memory Characteristics Table 22.40 shows the flash memory characteristics. Table 22.40 Flash Memory Characteristics (1) Conditions: V = 4.5 to 5.5 V, AV = 4.5 to 5.5 V, V = AV = 0 V, = 0°C to +75°C (operating temperature range for programming/erasing) Item Symbol Unit...
Page 744 Notes: 1. Make each time setting in accordance with the program/program-verify flowchart or erase/erase-verify flowchart. 2. Programming time per 128 bytes (Shows the total period for which the P-bit in the flash memory control register (FLMCR1) is set. It does not include the programming verification time.) 3.
Page 745 Table 22.40 Flash Memory Characteristics (2) — Preliminary — Conditions: V = 3.0 to 3.6 V, AV = 3.0 to 3.6 V, V = AV = 0 V = 0°C to +75°C (operating temperature range for programming/erasing) Item Symbol Unit Notes Programming time* —...
Page 746 Notes: 1. Make each time setting in accordance with the program/program-verify flowchart or erase/erase-verify flowchart. 2. Programming time per 128 bytes (Shows the total period for which the P-bit in the flash memory control register (FLMCR) is set. It does not include the programming verification time.) 3.
Page 747: Operational Timing
22.5 Operational Timing This section shows timing diagrams. 22.5.1 Clock Timing Clock timing is shown as follows: • Oscillator settling timing Figure 22.13 shows the oscillator settling timing. φ STBY OSC1 OSC1 Figure 22.13 Oscillator Settling Timing...
Page 748: Control Signal Timing
22.5.2 Control Signal Timing Control signal timing is shown as follows: • Reset input timing Figure 22.14 shows the reset input timing. • Reset output timing* Figure 22.15 shows the reset output timing. • Interrupt input timing Figure 22.16 shows the interrupt input timing for NMI and IRQ to IRQ φ...
Page 749 φ NMIS NMIH NMIS NMIH NMIS IRQ : Edge-sensitive IRQ : Level-sensitive IRQ (i = 0 to 5) NMIW (j = 0 to 5) Figure 22.16 Interrupt Input Timing...
Page 750: Bus Timing
22.5.3 Bus Timing Bus timing is shown as follows: • Basic bus cycle: two-state access Figure 22.17 shows the timing of the external two-state access cycle. • Basic bus cycle: three-state access Figure 22.18 shows the timing of the external three-state access cycle. •...
Page 751 φ to A PCH1 ACC3 ACC3 PCH2 (read) ACC1 to D (read) PCH1 HWR, LWR (write) WSW1 WDS1 to D (write) , CS , and RD. Note: Specification from the earliest negation timing of A to A Figure 22.17 Basic Bus Cycle: Two-State Access...
Page 752 φ to A ACC4 ACC4 (read) ACC2 to D (read) WSW2 HWR, LWR (write) WDS2 to D (write) Figure 22.18 Basic Bus Cycle: Three-State Access...
Page 753 φ to A RD (read) to D (read) HWR, LWR (write) to D (write) WAIT Figure 22.19 Basic Bus Cycle: Three-State Access with One Wait State φ BRQS BRQS BREQ BACD2 BACD1 BACK to A AS, RD, HWR, LWR Figure 22.20 Bus-Release Mode Timing...
Page 754: Tpc And I/O Port Timing
22.5.4 TPC and I/O Port Timing Figure 22.21 shows the TPC and I/O port input/output timing. φ Port 1 to B (read) Port 1 to 6, 8 to B (write) Figure 22.21 TPC and I/O Port Input/Output Timing 22.5.5 Timer Input/Output Timing 16-bit timer and 8-bit timer timing is shown below.
Page 755: Sci Input/Output Timing
TCKS φ TCKS TCLKA to TCLKD TCKWL TCKWH Figure 22.23 Timer External Clock Input Timing 22.5.6 SCI Input/Output Timing SCI timing is shown as follows: • SCI input clock timing Figure 22.24 shows the SCI input clock timing. • SCI input/output timing (synchronous mode) Figure 22.25 shows the SCI input/output timing in synchronous mode.
Page 756: Appendix A Instruction Set
Appendix A Instruction Set Instruction List Operand Notation Symbol Description General destination register General source register General register General destination register (address register or 32-bit register) General source register (address register or 32-bit register) General register (32-bit register) (EAd) Destination operand (EAs) Source operand Program counter...
Page 757 Condition Code Notation Symbol Description Changed according to execution result Undetermined (no guaranteed value) Cleared to 0 Set to 1 — Not affected by execution of the instruction ∆ Varies depending on conditions, described in notes...
Page 758: Data Transfer Instructions
Table A.1 Instruction Set 1. Data transfer instructions Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation H N Z #xx:8 → Rd8 MOV.B #xx:8, Rd — — 0 — Rs8 → Rd8 MOV.B Rs, Rd —...
Page 759 Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation H N Z @aa:24 → Rd16 MOV.W @aa:24, Rd — — 0 — Rs16 → @ERd MOV.W Rs, @ERd — — 0 — Rs16 → @(d:16, ERd) MOV.W Rs, @(d:16, —...
Page 760: Arithmetic Instructions
— — 0 — ERn32 → @SP MOVFPE @aa:16, Cannot be used in the Cannot be used in the H8/3062 Series H8/3062 Series MOVTPE Rs, Cannot be used in the Cannot be used in the @aa:16 H8/3062 Series H8/3062 Series 2.
Page 761 Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation H N Z ERd32+1 → ERd32 INC.L #1, ERd — — — ERd32+2 → ERd32 INC.L #2, ERd — — — DAA Rd Rd8 decimal adjust — * * —...
Page 762 Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation H N Z ERd32 ÷ Rs16 → ERd32 — — (6) (7) — — DIVXU. W Rs, ERd (Ed: remainder, Rd: quotient) (unsigned division) Rd16 ÷ Rs8 → Rd16 —...
Page 763 3. Logic instructions Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation H N Z Rd8∧#xx:8 → Rd8 AND.B #xx:8, Rd — — 0 — Rd8∧Rs8 → Rd8 AND.B Rs, Rd — — 0 — Rd16∧#xx:16 → Rd16 AND.W #xx:16, Rd —...
Page 764 4. Shift instructions Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation H N Z SHAL.B Rd — — SHAL.W Rd — — SHAL.L ERd — — SHAR.B Rd — — SHAR.W Rd — — SHAR.L ERd —...
Page 765: Bit Manipulation Instructions
5. Bit manipulation instructions Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation H N Z (#xx:3 of Rd8) ← 1 BSET #xx:3, Rd — — — — — — (#xx:3 of @ERd) ← 1 BSET #xx:3, @ERd —...
Page 766 Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation H N Z (#xx:3 of @ERd) → C BLD #xx:3, @ERd — — — — — (#xx:3 of @aa:8) → C BLD #xx:3, @aa:8 — — — — — ¬(#xx:3 of Rd8) →...
Page 767 6. Branching instructions Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Branch Mnemonic Operation Condition H N Z BRA d:8 (BT d:8) — If condition Always — — — — — — is true then BRA d:16 (BT d:16) —...
Page 768 Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Branch Mnemonic Operation Operation Condition H N Z Z ∨ (N⊕V) = 1 BLE d:8 — If condition — — — — — — is true then BLE d:16 —...
Page 769 7. System control instructions Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation H N Z PC → @–SP TRAPA #x:2 — 1 — — — — — 14 16 CCR → @–SP <vector> → PC CCR ←...
Page 770 8. Block transfer instructions Addressing Mode and No. of Instruction Length (bytes) States* Condition Code Mnemonic Operation H N Z if R4L ≠ 0 EEPMOV. B — — — — — — — 8+4n* repeat @R5 → @R6 R5+1 → R5 R6+1 →...
Page 771: Operation Code Maps
Operation Code Maps Table A.2 Operation Code Map (1)
Page 772 Table A.2 Operation Code Map (2)
Page 773 Table A.2 Operation Code Map (3)
Page 774: Number Of States Required For Execution
Number of States Required for Execution The tables in this section can be used to calculate the number of states required for instruction execution by the H8/300H CPU. Table A.4 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. Table A.3 indicates the number of states required per cycle according to the bus size.
Page 775 Table A.3 Number of States per Cycle Access Conditions External Device On-Chip Sup- porting Module 8-Bit Bus 16-Bit Bus On-Chip 8-Bit 16-Bit 2-State 3-State 2-State 3-State Cycle Memory Access Access Access Access Instruction fetch 6 + 2m 3 + m Branch address read S Stack operation Byte data access...
Page 776 Table A.4 Number of Cycles per Instruction Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W #xx:16, Rd ADD.W Rs, Rd ADD.L #xx:32, ERd ADD.L ERs, ERd ADDS ADDS #1/2/4, ERd ADDX...
Page 777 Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BRA d:16 (BT d:16) BRN d:16 (BF d:16) BHI d:16 BLS d:16 BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16...
Page 778 Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BNOT BNOT #xx:3, Rd BNOT #xx:3, @ERd BNOT #xx:3, @aa:8 BNOT Rn, Rd BNOT Rn, @ERd BNOT Rn, @aa:8 BOR #xx:3, Rd BOR #xx:3, @ERd BOR #xx:3, @aa:8 BSET BSET #xx:3, Rd...
Page 779 Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic DEC.B Rd DEC.W #1/2, Rd DEC.L #1/2, ERd DIVXS DIVXS.B Rs, Rd DIVXS.W Rs, ERd DIVXU DIVXU.B Rs, Rd DIVXU.W Rs, ERd EEPMOV EEPMOV.B 2n + 2* EEPMOV.W...
Page 780 Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @ERs, Rd MOV.B @(d:16, ERs), Rd MOV.B @(d:24, ERs), Rd MOV.B @ERs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B @aa:24, Rd MOV.B Rs, @ERd...
Page 781 Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic MOVFPE MOVFPE @aa:16, Rd* MOVTPE MOVTPE Rs, @aa:16* MULXS MULXS.B Rs, Rd MULXS.W Rs, ERd MULXU MULXU.B Rs, Rd MULXU.W Rs, ERd NEG.B Rd NEG.W Rd NEG.L ERd NOT.B Rd...
Page 782 XOR.L #xx:32, ERd XOR.L ERs, ERd XORC XORC #xx:8, CCR Notes: 1. n is the value set in register R4L or R4. The source and destination are accessed n + 1 times each. 2. Not available in the H8/3062 Series.
Page 783: Appendix B Internal I/O Registers
Appendix B Internal I/O Registers Table B.1 Comparison of H8/3062 Series Internal I/O Register Specifications H8/3062 Mask ROM Version, H8/3062 H8/3061 Mask H8/3062 F-ZTAT ROM Version, F-ZTAT Address H8/3062 R-Mask H8/3060 Mask H8/3064 A-Mask (Low) F-ZTAT Version ROM Version F-ZTAT...
Page 784: Address List (H8/3062F-Ztat, H8/3062F-Ztat R-Mask Version, H8/3062 Mask Rom Version, H8/3061 Mask Rom Version, H8/3060 Mask Rom Version)
Address List (H8/3062F-ZTAT, H8/3062F-ZTAT R-Mask Version, H8/3062 Mask ROM Version, H8/3061 Mask ROM Version, H8/3060 Mask ROM Version) Bit Names Data Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...
Page 785 Bit Names Data Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'EE020 ABWCR ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 Bus controller H'EE021 ASTCR AST7 AST6 AST5...
Page 786 Bit Names Data Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'EE044 — — — — — — — — — H'EE045 — — — —...
Page 787 Bit Names Data Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'EE068 — — — — — — — — — H'EE069 — — — —...
Page 788 Bit Names Data Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'FFF2A Reserved area (access prohibited) H'FFF2B H'FFF2C H'FFF2D H'FFF2E H'FFF2F H'FFF30 H'FFF31 H'FFF32 H'FFF33 H'FFF34 H'FFF35 H'FFF36...
Page 789 Bit Names Data Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'FFF4E — — — — — — — — — H'FFF4F — — — —...
Page 790 Bit Names Data Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'FFF70 16TCR1 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 16-bit timer channel 1 H'FFF71 TIOR1 —...
Page 791 Bit Names Data Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'FFF90 8TCR2 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 8-bit timer channels 2 and 3 H'FFF91 8TCR3 CMIEB CMIEA...
Page 792 Bit Names Data Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'FFFB0 SMR STOP CKS1 CKS0 SCI channel 0 H'FFFB1 BRR H'FFFB2 SCR MPIE TEIE CKE1 CKE0 H'FFFB3 TDR...
Page 793 Bit Names Data Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'FFFD3 P4DR Port 4 H'FFFD4 P5DR — — — — Port 5 H'FFFD5 P6DR Port 6 H'FFFD6 P7DR Port 7...
Page 794: Address List (H8/3064F-Ztat)
Address List (H8/3064F-ZTAT) Bit Names Data Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'EE000 P1DDR DDR P1 DDR P1 DDR P1 DDR P1 DDR P1 DDR P1 DDR P1 DDR Port 1...
Page 795 Bit Names Data Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'EE020 ABWCR ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 Bus controller H'EE021 ASTCR AST7 AST6 AST5...
Page 796 Bit Names Data Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'EE044 — — — — — — — — — H'EE045 — — — —...
Page 797 Bit Names Data Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'EE068 — — — — — — — — — H'EE069 — — — —...
Page 798 Bit Names Data Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'FFF2A Reserved area (access prohibited) H'FFF2B H'FFF2C H'FFF2D H'FFF2E H'FFF2F H'FFF30 H'FFF31 H'FFF32 H'FFF33 H'FFF34 H'FFF35 H'FFF36...
Page 799 Bit Names Data Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'FFF4E — — — — — — — — — H'FFF4F — — — —...
Page 800 Bit Names Data Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'FFF70 16TCR1 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 16-bit timer channel 1 H'FFF71 TIOR1 —...
Page 801 Bit Names Data Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'FFF90 8TCR2 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 8-bit timer channels 2 and 3 H'FFF91 8TCR3 CMIEB CMIEA...
Page 802 Bit Names Data Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'FFFB0 SMR STOP CKS1 CKS0 SCI channel 0 H'FFFB1 BRR H'FFFB2 SCR MPIE TEIE CKE1 CKE0 H'FFFB3 TDR...
Page 803 Bit Names Data Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'FFFD3 P4DR Port 4 H'FFFD4 P5DR — — — — Port 5 H'FFFD5 P6DR Port 6 H'FFFD6 P7DR Port 7...
Page 804: Address List (H8/3062F-Ztat A-Mask Version)
Address List (H8/3062F-ZTAT A-Mask Version) Bit Names Data Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'EE000 P1DDR DDR P1 DDR P1 DDR P1 DDR P1 DDR P1 DDR P1 DDR P1...
Page 805 Bit Names Data Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'EE020 ABWCR ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 Bus controller H'EE021 ASTCR AST7 AST6 AST5...
Page 806 Bit Names Data Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'EE044 — — — — — — — — — H'EE045 — — — —...
Page 807 Bit Names Data Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'EE068 — — — — — — — — — H'EE069 — — — —...
Page 808 Bit Names Data Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'FFF2A Reserved area (access prohibited) H'FFF2B H'FFF2C H'FFF2D H'FFF2E H'FFF2F H'FFF30 H'FFF31 H'FFF32 H'FFF33 H'FFF34 H'FFF35 H'FFF36...
Page 809 Bit Names Data Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'FFF4E — — — — — — — — — H'FFF4F — — — —...
Page 810 Bit Names Data Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'FFF70 16TCR1 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 16-bit timer channel 1 H'FFF71 TIOR1 —...
Page 811 Bit Names Data Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'FFF90 8TCR2 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 8-bit timer channels 2 and 3 H'FFF91 8TCR3 CMIEB CMIEA...
Page 812 Bit Names Data Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'FFFB0 SMR STOP CKS1 CKS0 SCI channel 0 H'FFFB1 BRR H'FFFB2 SCR MPIE TEIE CKE1 CKE0 H'FFFB3 TDR...
Page 813 Bit Names Data Address Register (Low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'FFFD3 P4DR Port 4 H'FFFD4 P5DR — — — — Port 5 H'FFFD5 P6DR Port 6 H'FFFD6 P7DR Port 7...
Page 814: Functions
Functions Register abbreviation Address to which register is mapped Register name Name of on-chip supporting module TIER—Timer Interrupt Enable Register H' 90 Bit numbers ICIAE ICIBE ICICE OCIDE OCIAE OCIBE OVIE Initial bit values Names of the bits. Initial value Dashes (—) indicate R/W: reserved bits.
Page 815 P1DDR—Port 1 Data Direction Register H’EE000 Port 1 Initial value Modes 1 to 4 Read/Write Initial value Modes 5 to 7 Read/Write Port 1 input/output select Generic input Generic output P2DDR—Port 2 Data Direction Register H’EE001 Port 2 Initial value Modes 1 to 4 Read/Write Initial value...
Page 816 P3DDR—Port 3 Data Direction Register H’EE002 Port 3 Initial value Read/Write Port 3 input/output select Generic input Generic output P4DDR—Port 4 Data Direction Register H’EE003 Port 4 Initial value Read/Write Port 4 input/output select Generic input Generic output...
Page 817 P5DDR—Port 5 Data Direction Register H’EE004 Port 5 Initial value Modes 1 to 4 Read/Write Initial value Modes 5 to 7 Read/Write Port 5 input/output select Generic input pin Generic output pin P6DDR—Port 6 Data Direction Register H’EE005 Port 6 Initial value Read/Write Port 6 input/output select...
Page 818 P8DDR—Port 8 Data Direction Register H’EE007 Port 8 Initial value Modes 1 to 4 Read/Write Initial value Modes 5 to 7 Read/Write Port 8 input/output select Generic input Generic output...
Page 819 P9DDR—Port 9 Data Direction Register H’EE008 Port 9 Initial value Read/Write Port 9 input/output select Generic input Generic output PADDR—Port A Data Direction Register H’EE009 Port A Initial value Modes 3, 4 Read/Write Modes Initial value 1, 2, 5, 6, 7 Read/Write Port A input/output select Generic input...
Page 820 MDCR—Mode Control Register H’EE011 System control MDS2 MDS1 MDS0 Initial value Read/Write Mode select 2 to 0 Bit 2 Bit 1 Bit 0 Operating Mode Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 Note: * Determined by the state of the mode pins (MD to MD...
Page 821 SYSCR—System Control Register H’EE012 System control SSBY STS2 STS1 STS0 NMIEG SSOE RAME Initial value Read/Write RAM enable On-chip RAM is disabled On-chip RAM is enabled Software standby output port enable In software standby mode, all address bus and bus control signals are high- impedance In software standby mode,...
Page 822 BRCR—Bus Release Control Register H’EE013 Bus controller A23E A22E A21E A20E BRLE Modes Initial value 1, 2, 6, 7 Read/Write Modes Initial value 3, 4 Read/Write Initial value Mode 5 Read/Write Bus release enable Address 23 to 20 enable The bus cannot be Address output released to an Other input/output...
Page 823 IER—IRQ Enable Register H’EE015 Interrupt Controller IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E Initial value Read/Write to IRQ enable to IRQ interrupts are disabled to IRQ interrupts are enabled ISR—IRQ Status Register H’EE016 Interrupt Controller IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial value Read/Write R/(W)*...
Page 824 IPRA—Interrupt Priority Register A H’EE018 Interrupt Controller IPRA7 IPRA6 IPRA5 IPRA4 IPRA3 IPRA2 IPRA1 IPRA0 Initial value Read/Write Priority level A7 to A0 Priority level 0 (low priority) Priority level 1 (high priority) • Interrupt sources controlled by each bit Bit 7 Bit 6 Bit 5...
Page 825 DASTCR—D/A Standby Control Register H’EE01A DASTE Initial value Read/Write D/A standby enable D/A output is disabled in software standby mode (Initial value) D/A output is enabled in software standby mode...
Page 826 DIVCR—Division Control Register H’EE01B System control DIV1 DIV0 Initial value Read/Write Division ratio bits 1 and 0 Bit 1 Bit 0 Frequency Division Ratio DIV1 DIV0 (Initial value)
Page 827 MSTCRH—Module Standby Control Register H H’EE01C System control PSTOP MSTPH1 MSTPH0 Initial value Read/Write Module standby H1 to H0 Selection bits for placing modules in standby state. Reserved bits φ clock stop Enables or disables ø clock output. MSTCRL—Module Standby Control Register L H’EE01D System control MSTPL4...
Page 828 Address update mode 2 is selected Address update mode 1 is selected (Initial value) Note: H8/3062F-ZTAT This register not provided H8/3062F-ZTAT R-mask version This register provided H8/3062F-ZTAT A-mask version H8/3064F-ZTAT H8/3062 mask ROM version H8/3061 mask ROM version H8/3060 mask ROM version...
Page 829 CSCR—Chip Select Control Register H’EE01F Bus controller CS7E CS6E CS5E CS4E Initial value Read/Write Chip select 7 to 4 enable Bit n Description CSnE Output of chip select signal CSn is disabled (Initial value) Output of chip select signal CSn is enabled (n = 7 to 4)
Page 830 ABWCR—Bus Width Control Register H’EE020 Bus controller ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 Modes 1, 3, 5, 6, Initial value and 7 Modes 2 and 4 Initial value Read/Write Area 7 to 0 bus width control Bits 7 to 0 Bus Width of Access Area ABW7 to ABW0...
Page 831 WCRH—Wait Control Register H H’EE022 Bus controller Initial value Read/Write Area 4 wait control 1 and 0 No program wait is inserted 1 program wait state is inserted 2 program wait states are inserted 3 program wait states are inserted Area 5 wait control 1 and 0 No program wait is inserted 1 program wait state is inserted...
Page 832 WCRL—Wait Control Register L H’EE023 Bus controller Initial value Read/Write Area 0 wait control 1 and 0 No program wait is inserted 1 program wait state is inserted 2 program wait states are inserted 3 program wait states are inserted Area 1 wait control 1 and 0 No program wait is inserted 1 program wait state is inserted...
Page 833 BCR—Bus Control Register H’EE024 Bus controller ICIS1 ICIS0 — — — — RDEA WAITE Initial value Read/Write — — — — Wait pin enable WAIT pin wait input is disabled WAIT pin wait input is enabled Area division unit select Area divisions are as follows: Area 0: 2 MB Area 4: 1.93 MB...
Page 834: Flash Memory
Note: Fix the FWE pin low in mode 6. H8/3062F-ZTAT This register provided H8/3062F-ZTAT R-mask version H8/3062F-ZTAT A-mask version This register provided (FLMCR1) H8/3064F-ZTAT H8/3062 mask ROM version This register not provided H8/3061 mask ROM version H8/3060 mask ROM version...
Page 835 Flash memory error Notes: Writes to FLMCR2 H8/3062F-ZTAT This register not are prohibited. provided H8/3062F-ZTAT R-mask version H8/3062F-ZTAT A-mask version This register provided H8/3064F-ZTAT H8/3062 mask ROM version This register not H8/3061 mask ROM version provided H8/3060 mask ROM version...
Page 836 A value of 1 cannot be set in this register in mode 6. H8/3062F-ZTAT This register provided H8/3062F-ZTAT R-mask version H8/3062F-ZTAT A-mask version This register provided (EBR1) H8/3064F-ZTAT H8/3062 mask ROM version This register not provided H8/3061 mask ROM version H8/3060 mask ROM version...
Page 837 A value of 1 cannot be set in this register in mode 6. H8/3062F-ZTAT This register not provided H8/3062F-ZTAT R-mask version H8/3062F-ZTAT A-mask version H8/3064F-ZTAT This register provided H8/3062 mask ROM version This register not provided H8/3061 mask ROM version H8/3060 mask ROM version...
Page 838 P4PCR—Port 4 Input Pull-Up Control Register H’EE03E Port 4 Initial value Read/Write Port 4 input pull-up control 7 to 0 Input pull-up transistor is off Input pull-up transistor is on Note: Valid when the corresponding P4DDR bit is cleared to 0 (designating generic input).
Page 839 1. H8/3062F-ZTAT This register provided H8/3062F-ZTAT R-mask version H8/3062F-ZTAT A-mask version H8/3064F-ZTAT This register provided (bit specification below) H8/3062 mask ROM version This register not provided H8/3061 mask ROM version H8/3060 mask ROM version...
Page 840 RAMCR (H8/3064F-ZTAT)—RAM Control Register H'EE077 Flash Memory — — — — RAMS RAM2 RAM1 RAM0 Modes Initial value 1 to 4 — — — — Modes Initial value 5 to 7 — — — — Reserved bits...
Page 841 Before the exception handling stack or vector read is performed. H8/3062F-ZTAT This register provided H8/3062F-ZTAT R-mask version H8/3062F-ZTAT A-mask version This register not provided (FLER bit in FLMCR2) H8/3064F-ZTAT H8/3062 mask ROM version This register not provided H8/3061 mask ROM version H8/3060 mask ROM version...
Page 842 TSTR—Timer Start Register H’FFF60 16-bit timer (all channels) — — — — — STR2 STR1 STR0 Initial value Read/Write — — — — — Reserved bits Counter start 0 16TCNT0 is halted (Initial value) 16TCNT0 is counting Counter start 1 16TCNT1 is halted (Initial value) 16TCNT1 is counting...
Page 843 TSNC—Timer Synchro Register H’FFF61 16-bit timer (all channels) — — — — — SYNC2 SYNC1 SYNC0 Initial value Read/Write — — — — — Reserved bits Timer sync 0 Channel 0 timer counter (16TCNT0) operates independently (16TCNT0 presetting/clearing is independent of other channels) (Initial value) Channel 0 operates synchronously Synchronous presetting/synchronous clearing...
Page 844 TMDR—Timer Mode Register H’FFF62 16-bit timer (all channels) — FDIR — — PWM2 PWM1 PWM0 Initial value Read/Write — — — PWM mode 0 Channel 0 operates normally (Initial value) Channel 0 operates in PWM mode PWM mode 1 Channel 1 operates normally (Initial value) Channel 1 operates in PWM mode PWM mode 2...
Page 845 TOLR—Timer Output Level Setting Register H’FFF63 16-bit timer (all channels) — — TOB2 TOA2 TOB1 TOA1 TOB0 TOA0 Initial value Read/Write — — Output level setting A0 TIOCA is 0 (Initial value) TIOCA is 1 Output level setting B0 TIOCB is 0 (Initial value) TIOCB...
Page 846 TISRA—Timer Interrupt Status Register A H’FFF64 16-bit timer (all channels) Bit: — IMIEA2 IMIEA1 IMIEA0 — IMFA2 IMFA1 IMFA0 Initial value: Read/Write: — — R/(W)* R/(W)* R/(W)* Input capture/compare match flag A0 [Clearing conditions] (Initial value) Read IMFA0 when IMFA0=1, then write 0 in IMFA0 [Setting conditions] •...
Page 847 TISRB—Timer Interrupt Status Register B H’FFF65 16-bit timer (all channels) Bit: — IMIEB2 IMIEB1 IMIEB0 — IMFB2 IMFB1 IMFB0 Initial value: Read/Write: — — R/(W)* R/(W)* R/(W)* Input capture/compare match flag B0 [Clearing condition] (Initial value) Read IMFB0 when IMFB0=1, then write 0 in IMFB0. [Setting conditions] 16TCNT0=GRB0 when GRB0 functions as an output compare register.
Page 848 TISRC—Timer Interrupt Status Register C H’FFF66 16-bit timer (all channels) Bit: — OVIE2 OVIE1 OVIE0 — OVF2 OVF1 OVF0 Initial value: Read/Write: — — R/(W)* R/(W)* R/(W)* Overflow flag 0 [Clearing condition] (Initial value) Read OVF0 when OVF0 = 1, then write 0 in OVF0. [Setting condition] 16TCNT0 overflowed from H'FFFF to H'0000.
Page 849 16TCR0—Timer Control Register 0 H’FFF68 16-bit timer channel 0 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value Read/Write — Timer prescaler 2 to 0 Bit 2 Bit 1 Bit 0 Description TPSC2 TPSC1 TPSC0 (Initial value) Internal clock : ø Internal clock : ø...
Page 850 TIOR0—Timer I/O Control Register 0 H’FFF69 16-bit timer channel 0 Bit: — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 Initial value: Read/Write: — — I / O control A2 to A0 Bit 2 Bit 1 Bit 0 Description IOA2 IOA1 IOA0 GRA is an output No output at compare match...
Page 851 16TCNT0 H/L—Timer Counter 0 H/L H’FFF6A, H’FFF6B 16-bit timer channel 0 Initial value Read/Write Up - counter GRA0 H/L—General Register A0 H/L H’FFF6C, H’FFF6D 16-bit timer channel 0 Initial value Read/Write Output compare or input capture register GRB0 H/L—General Register B0 H/L H’FFF6E, H’FFF6F 16-bit timer channel 0 Initial value...
Page 852 16TCR1 Timer Control Register 1 H’FFF70 16-bit timer channel 1 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value Read/Write — *Bit functions are the same as for 16-bit timer channel 0. TIOR1—Timer I/O Control Register 1 H’FFF71 16-bit timer channel 1 —...
Page 853 GRA1 H/L—General Register A1 H/L H’FFF74, H’FFF75 16-bit timer channel 1 Initial value Read/Write *Bit functions are the same as for 16-bit timer channel 0. GRB1 H/L—General Register B1 H/L H’FFF76, H’FFF77 16-bit timer channel 1 Initial value Read/Write *Bit functions are the same as for 16-bit timer channel 0. 16TCR2 Timer Control Register 2 H’FFF78 16-bit timer channel 2...
Page 854 TIOR2—Timer I/O Control Register 2 H’FFF79 16-bit timer channel 2 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 Initial value Read/Write — — *Bit functions are the same as for 16-bit timer channel 0. 16TCNT2 H/L—Timer Counter 2 H/L H’FFF7A, H’FFF7B 16-bit timer channel 2 Initial value Read/Write...
Page 855 GRB2 H/L—General Register B2 H/L H’FFF7E, H’FFF7F 16-bit timer channel 2 Initial value Read/Write *Bit functions are the same as for 16-bit timer channel 0.
Page 856 8TCR0—Timer Control Register 0 H’FFF80 8-bit timer channel 0 8TCR1—Timer Control Register 1 H’FFF81 8-bit timer channel 1 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Initial value Read/Write Clock select 2 to 0 Clock input is disabled Internal clock: counted on rising edge of φ/8 Internal clock: counted on rising edge of φ/64...
Page 857 8TCSR0—Timer Control/Status Register 0 H’FFF82 8-bit timer channel 0 CMFB CMFA ADTE OIS3 OIS2 Initial value Read/Write R/(W)* R/(W)* R/(W)* Output select A1 and A0 Bit 1 Bit 0 Description No change at compare match A 0 output at compare match A 1 output at compare match A Output toggles at compare match A...
Page 858 8TCSR1—Timer Control/Status Register 1 H’FFF83 8-bit timer channel 1 CMFB CMFA OIS3 OIS2 Initial value Read/Write R/(W)* R/(W)* R/(W)* Output select A1 and A0 Bit 1 Bit 0 Description No change at compare match A 0 output at compare match A 1 output at compare match A Output toggles at compare match A...
Page 859 TCORA0—Time Constant Register A0 H’FFF84 8-bit timer channel 0 TCORA1—Time Constant Register A1 H’FFF85 8-bit timer channel 1 TCORA0 TCORA1 Initial value Read/Write TCORB0—Time Constant Register B0 H’FFF86 8-bit timer channel 0 TCORB1—Time Constant Register B1 H’FFF87 8-bit timer channel 1 TCORB0 TCORB1 Initial value...
Page 860 TCSR—Timer Control/Status Register H’FFF8C WT/IT CKS2 CKS1 CKS0 Initial value Read/Write R/(W)* Clock select 2 to 0 CKS2 CKS1 CKS0 Description φ/2 φ/32 φ/64 φ/128 φ/256 φ/512 φ/2048 φ/4096 Timer enable Timer disabled • TCNT is initialized to H'00 and halted Timer enabled •...
Page 861 TCNT—Timer Counter H'FFF8D (read), H'FFF8C (write) Initial value Read/Write Count value RSTCSR—Reset Control/Status Register H'FFF8F (read), H'FFF8E (write) WRST RSTOE Initial value Read/Write R/(W)* Reset output enable External output of reset signal is disabled External output of reset signal is enabled Watchdog timer reset [Clearing conditions] •...
Page 862 8TCR2—Timer Control Register 2 H’FFF90 8-bit timer channel 2 8TCR3—Timer Control Register 3 H’FFF91 8-bit timer channel 3 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Initial value Read/Write Clock select 2 to 0 CSK2 CSK1 CSK0 Description Clock input is disabled Internal clock: counted on rising edge of φ/8 Internal clock: counted on rising edge...
Page 863 8TCSR2—Timer Control/Status Register 2 H’FFF92 8-bit timer channel 2 8TCSR3—Timer Control/Status Register 3 H’FFF93 8-bit timer channel 3 8TCSR2 CMFB CMFA OIS3 OIS2 Initial value Read/Write R/(W)* R/(W)* R/(W)* — 8TCSR3 CMFB CMFA OIS3 OIS2 Initial value Read/Write R/(W)* R/(W)* R/(W)* Output select A1 and A0 Bit 1...
Page 864 TCORA2—Time Constant Register A2 H’FFF94 8-bit timer channel 2 TCORA3—Time Constant Register A3 H’FFF95 8-bit timer channel 3 TCORA2 TCORA3 Initial value Read/Write TCORB2—Time Constant Register B2 H’FFF96 8-bit timer channel 2 TCORB3—Time Constant Register B3 H’FFF97 8-bit timer channel 3 TCORB2 TCORB3 Initial value...
Page 865 DADR0—D/A Data Register 0 H’FFF9C Initial value Read/Write D/A conversion data DADR1—D/A Data Register 1 H’FFF9D Initial value Read/Write D/A conversion data...
Page 866 DACR—D/A Control Register H’FFF9E DAOE1 DAOE0 Initial value Read/Write D/A enable Bit 7 Bit 6 Bit 5 Description DAOE1 DAOE0 D/A conversion is disabled in channels 0 and 1 D/A conversion is enabled in channel 0 D/A conversion is disabled in channel 1 D/A conversion is enabled in channels 0 and 1...
Page 867 TPMR—TPC Output Mode Register H’FFFA0 G3NOV G2NOV G1NOV G0NOV Initial value Read/Write Group 0 non-overlap Normal TPC output in group 0. Output values change at compare match A in the selected 16-bit timer channel Non-overlapping TPC output in group 0, controlled by compare match A and B in the selected 16-bit timer channel Group 1 non-overlap...
Page 868 TPCR—TPC Output Control Register H’FFFA1 G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value Read/Write Group 0 compare match select 1 and 0 Bit 1 Bit 0 16-Bit Timer Channel Selected as Output Trigger G0CMS1 G0CMS0 TPC output group 0 (TP to TP ) is triggered by compare match in 16-bit timer channel 0...
Page 869 NDERB—Next Data Enable Register B H’FFFA2 NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial value Read/Write Next data enable 15 to 8 Bits 7 to 0 Description NDER15 to NDER8 TPC outputs TP to TP are disabled (NDR15 to NDR8 are not transferred to PB to PB TPC outputs TP to TP...
Page 870 NDRB—Next Data Register B H’FFFA4/H’FFFA6 • Same trigger for TPC output groups 2 and 3  Address H'FFFA4 NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 Initial value Read/Write Store the next output data for TPC output group 3 Store the next output data for TPC output group 2 ...
Page 871 NDRA—Next Data Register A H’FFFA5/H’FFFA7 • Same trigger for TPC output groups 0 and 1  Address H'FFFA5 NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 Initial value Read/Write Store the next output data for TPC output group 1 Store the next output data for TPC output group 0 ...
Page 872 SMR—Serial Mode Register H’FFFB0 SCI0 STOP CKS1 CKS0 Initial value Read/Write Clock select 1 and 0 Bit 1 Bit 0 Clock Source CKS1 CKS0 φ clock φ/4 clock φ/16 clock φ/64 clock Multiprocessor mode Multiprocessor function disabled Multiprocessor format selected Stop bit length One stop bit Two stop bits...
Page 873 BRR—Bit Rate Register H’FFFB1 SCI0 Initial value Read/Write Serial communication bit rate setting...
Page 874 SCR—Serial Control Register H’FFFB2 SCI0 MPIE TEIE CKE1 CKE0 Initial value Read/Write Clock enable 1 and 0 Receive enable (for serial communication interface) Receiving is Bit 1 Bit 0 Description disabled CKE1 CKE0 Receiving is Internal clock: SCK pin Asynchronous mode enabled available for generic I/O Internal clock: SCK pin...
Page 875 TDR—Transmit Data Register H’FFFB3 SCI0 Initial value Read/Write Serial transmit data...
Page 876 SSR—Serial Status Register H’FFFB4 SCI0 TDRE RDRF ORER FER/ERS TEND MPBT Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Multiprocessor bit transfer Multiprocessor bit value in transmit data is 0 Multiprocessor bit value in transmit data is 1 Multiprocessor bit Multiprocessor bit value in receive data is 0 Multiprocessor bit value in receive data is 1 Transmit end (for serial communication interface)
Page 877 RDR—Receive Data Register H’FFFB5 SCI0 Initial value Read/Write Serial receive data...
Page 878 SCMR—Smart Card Mode Register H’FFFB6 SCI0 SDIR SINV SMIF Initial value Read/Write Smart card interface mode select Smart card interface function is disabled (Initial value) Smart card interface function is enabled Smart card data invert Unmodified TDR contents are transmitted (Initial value) Receive data is stored unmodified in RDR Inverted 1/0 logic levels of TDR contents are transmitted...
Page 879 SMR—Serial Mode Register H’FFFB8 SCI1 STOP CKS1 CKS0 Initial value Read/Write Note: Bit functions are the same as for SCI0. BRR—Bit Rate Register H’FFFB9 SCI1 Initial value Read/Write Note: Bit functions are the same as for SCI0. SCR—Serial Control Register H’FFFBA SCI1 MPIE...
Page 880 TDR—Transmit Data Register H’FFFBB SCI1 Initial value Read/Write Note: Bit functions are the same as for SCI0. SSR—Serial Status Register H’FFFBC SCI1 TDRE RDRF ORER FER/ERS TEND MPBT Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: Bit functions are the same as for SCI0. * Only 0 can be written to clear the flag.
Page 881 SCMR—Smart Card Mode Register H’FFFBE SCI1 SDIR SINV SMIF Initial value Read/Write Note: Bit functions are the same as for SCI0.
Page 882 P1DR—Port 1 Data Register H’FFFD0 Port 1 Initial value Read/Write Data for port 1 pins P2DR—Port 2 Data Register H’FFFD1 Port 2 Initial value Read/Write Data for port 2 pins P3DR—Port 3 Data Register H’FFFD2 Port 3 Initial value Read/Write Data for port 3 pins...
Page 883 P4DR—Port 4 Data Register H’FFFD3 Port 4 Initial value Read/Write Data for port 4 pins P5DR—Port 5 Data Register H’FFFD4 Port 5 Initial value Read/Write Data for port 5 pins P6DR—Port 6 Data Register H’FFFD5 Port 6 Initial value Read/Write Data for port 6 pins...
Page 884 P7DR—Port 7 Data Register H’FFFD6 Port 7 Initial value Read/Write Data for port 7 pins Note: * Determined by pins P7 to P7 P8DR—Port 8 Data Register H’FFFD7 Port 8 Initial value Read/Write Data for port 8 pins...
Page 885 P9DR—Port 9 Data Register H’FFFD8 Port 9 Initial value Read/Write Data for port 9 pins PADR—Port A Data Register H’FFFD9 Port A Initial value Read/Write Data for port A pins PBDR—Port B Data Register H’FFFDA Port B Initial value Read/Write Data for port B pins...
Page 886 ADDRA H/L—A/D Data Register A H/L H’FFFE0, H’FFFE1 Initial value Read/Write ADDRAH ADDRAL A/D conversion data 10-bit data giving an A/D conversion result ADDRB H/L—A/D Data Register B H/L H’FFFE2, H’FFFE3 Initial value Read/Write ADDRBH ADDRBL A/D conversion data 10-bit data giving an A/D conversion result...
Page 887 ADDRC H/L—A/D Data Register C H/L H’FFFE4, H’FFFE5 Initial value Read/Write ADDRCH ADDRCL A/D conversion data 10-bit data giving an A/D conversion result ADDRD H/L—A/D Data Register D H/L H’FFFE6, H’FFFE7 Initial value Read/Write ADDRDH ADDRDL A/D conversion data 10-bit data giving an A/D conversion result ADCR—A/D Control Register H’FFFE9 TRGE...
Page 888 ADCSR—A/D Control/Status Register H’FFFE8 ADIE ADST SCAN Initial value Read/Write R/(W)* Channel select 2 to 0 Clock select Conversion time = Description Group Selection Channel Selection 134 states (maximum) CH1 CH0 Single Mode Scan Mode Conversion time = 70 states (maximum) to AN to AN Scan mode...
Page 889 Appendix C I/O Port Block Diagrams Port 1 Block Diagram Software SSOE standby Mode 6/7 Hardware standby External bus released Reset Mode 1 to 4 P1 DDR WP1D Reset Mode 6/7 P1 DR Mode 1 to 5 WP1D: Write to P1DDR WP1: Write to port 1 RP1:...
Page 890 Port 2 Block Diagram Software Reset standby SSOE P2 PCR RP2P WP2P Mode 6/7 Hardware standby Reset External bus Mode 1 to 4 released P2 DDR WP2D Reset Mode 6/7 P2 DR Mode 1 to 5 WP2P: Write to P2PCR RP2P: Read P2PCR WP2D:...
Page 891 Port 3 Block Diagram Reset Hardware standby External Mode 6/7 bus released P3 DDR Write to external address WP3D Reset Mode 6/7 P3 DR Mode 1 to 5 Read external address WP3D: Write to P3DDR WP3: Write to port 3 RP3: Read port 3 n = 0 to 7...
Page 892 Port 4 Block Diagram 8-bit bus 16-bit bus mode mode Mode Mode 6/7 1 to 5 Reset P4 PCR RP4P WP4P Hardware Reset standby Write to external address P4 DDR External bus released WP4D Reset P4 DR Read external address WP4P: Write to P4PCR RP4P:...
Page 893 Port 5 Block Diagram Software standby SSOE Reset P5 PCR RP5P WP5P Mode 6/7 Hardware standby External bus released Mode 1 to 4 Reset P5 DDR WP5D Reset Mode 6/7 P5 DR Mode 1 to 5 WP5P: Write to P5PCR RP5P: Read P5PCR WP5D:...
Page 894 Port 6 Block Diagrams Reset Hardware Standby P6 DDR Bus controller WAIT WP6D Mode 6/7 input Reset enable P6 DR Bus controller WAIT WP6D: Write to P6DDR input WP6: Write to port 6 RP6: Read port 6 Figure C.6 (a) Port 6 Block Diagram (Pin P6...
Page 895 Reset controller Hardware Standby P6 DDR Mode 6/7 WP6D Bus release enable Reset P6 DR BREQ input WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6 Figure C.6 (b) Port 6 Block Diagram (Pin P6...
Page 896 Reset Hardware standby P6 DDR WP6D Reset P6 DR Bus controller Mode 6/7 Bus release enable BACK output WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6 Figure C.6 (c) Port 6 Block Diagram (Pin P6...
Page 897 SSOE Software standby Mode 6/7 Hardware standby External bus released Reset P6 DDR Mode 6/7 WP6D Reset Mode 6/7 P6 DR Mode 1 to 5 Bus controller AS output RD output HWR output LWR output WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6...
Page 898 Hardware standby φ output enable φ output RP6: Read port 6 Figure C.6 (e) Port 6 Block Diagram (Pin P6...
Page 899 Port 7 Block Diagrams A/D converter Analog input Input enable RP7: Read port 7 Channel select signal n = 0 to 5 Figure C.7 (a) Port 7 Block Diagram (Pins P7 to P7 A/D converter Analog input Input enable Channel select signal D/A converter Output enable Analog output...
Page 900 Port 8 Block Diagrams Reset P8 DDR WP8D Reset P8 DR Interrupt controller WP8D: Write to P8DDR WP8: Write to port 8 input RP8: Read port 8 Figure C.8 (a) Port 8 Block Diagram (Pin P8...
Page 901 Mode 6/7 SSOE Software standby External bus released Reset Hardware standby Bus controller P8 DDR WP8D Reset output Mode 6/7 P8 DR Mode 1 to 5 Interrupt controller input WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 SSOE: Software standby output port enable n = 1, 2...
Page 902 Mode 6/7 Software standby SSOE External bus released Reset Hardware standby Bus controller WP8D output Reset Mode 6/7 Mode 1 to 5 Interrupt controller input A/D converter ADTRG input WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 SSOE: Software standby output port enable Figure C.8 (c) Port 8 Block Diagram (Pin P8...
Page 903 Mode 6/7 Software standby SSOE External bus released Reset Mode 1 to 4 Bus controller P8 DDR Hardware standby WP8D output Reset Mode 6/7 P8 DR Mode 1 to 5 WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 SSOE: Software standby output port enable...
Page 904 Port 9 Block Diagrams Reset Hardware standby P9 DDR WP9D Reset P9 DR Output enable Serial transmit data Guard time WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C.9 (a) Port 9 Block Diagram (Pin P9...
Page 905 Reset Hardware standby P9 DDR WP9D Reset P9 DR Output enable Serial transmit data Guard time WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C.9 (b) Port 9 Block Diagram (Pin P9...
Page 906 Reset Hardware standby P9 DDR WP9D Input enable Reset P9 DR Serial receive data WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C.9 (c) Port 9 Block Diagram (Pin P9...
Page 907 Reset Hardware standby WP9D Input enable Reset Serial receive data WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C.9 (d) Port 9 Block Diagram (Pin P9...
Page 908 Reset Hardware standby P9 DDR WP9D Clock input Reset enable P9 DR Clock output enable Clock output Clock input WP9D: Write to P9DDR Interrupt WP9: Write to port 9 controller RP9: Read port 9 input Figure C.9 (e) Port 9 Block Diagram (Pin P9...
Page 909 Reset Hardware standby WP9D Clock input enable Reset Clock output enable Clock output Clock input Interrupt controller input WP9D : Write to P9DDR : Write to port 9 : Read port 9 Figure C.9 (f) Port 9 Block Diagram (Pin P9...
Page 910 C.10 Port A Block Diagrams Reset Hardware standby PA DDR WPAD Reset output enable PA DR Next data Output trigger 16-bit timer Counter clock input WPAD: Write to PADDR WPA: Write to port A 8-bit timer RPA: Read port A n = 0 and 1 Counter clock input...
Page 911 Reset Hardware standby PA DDR WPAD Reset output enable PA DR Next data Output trigger 16-bit timer Output enable Compare match output Input capture Counter clock WPAD: Write to PADDR input WPA: Write to port A RPA: Read port A n = 2 and 3 8-bit timer Counter...
Page 912 Software standby SSOE Bus released Address output enable Mode 3/4 Reset Hardware standby WPAD Reset TPC output enable Next data Output trigger 16-bit timer Output enable Compare match output Input capture WPAD: Write to PADDR WPA: Write to port A RPA: Read port A SSOE:...
Page 913 C.11 Port B Block Diagrams Software standby SSOE Hardware standby Reset PB DDR Bus controller WPBD CS5 output Bus released CS output enable Reset Mode TPC output 1 to 5 enable PB DR Next data Output trigger 8-bit timer Output enable Compare match output WPBD:...
Page 914 Software standby SSOE Hardware standby Reset Bus controller WPBD CS4 output Bus released CS output enable Reset Mode 1 to 5 TPC output enable Next data Output trigger 8-bit timer Output enable Compare match output TMO2 TMO3 input WPBD: Write to PBDDR WPB: Write to port B RPB:...
Page 915 Reset Hardware standby PB DDR WPBD Reset TPC output enable PB DR Next data Output trigger WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B Figure C.11 (c) Port B Block Diagram (Pin PB...
Page 916 Reset Hardware standby WPBD Reset TPC output enable Next data Output trigger WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B Figure C.11 (d) Port B Block Diagram (Pin PB...
Page 917 Reset PB DDR Hardware standby WPBD Reset output enable PB DR Next data Output trigger WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B Figure C.11 (e) Port B Block Diagram (Pin PB...
Page 918 Reset Hardware standby PB DDR WPBD Reset output enable PB DR Next data Output trigger WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B Figure C.11 (f) Port B Block Diagram (Pin PB...
Page 919: Appendix D Pin States
Appendix D Pin States Port States in Each Mode Table D.1 Port States Hardware Standby Software Bus- Program Name Mode Reset Mode Standby Mode Released Mode Execution Mode RESO* — to P1 1 to 4 (SSOE = 0) to A (SSOE = 1) Keep (DDR = 0)
Page 920 Hardware Standby Software Bus- Program Name Mode Reset Mode Standby Mode Released Mode Execution, Mode (SSOE = 0) to A to P5 1 to 4 (SSOE = 1) Keep (DDR = 0) (DDR = 0) Keep Input port (DDR = 1) DDR=1,SSOE=0 to A DDR=1,SSOE=1...
Page 921 Hardware Standby Software Bus- Program Name Mode Reset Mode Standby Mode Released Mode Execution Mode 1 to 5 (DDR=0) (DDR=0) (DDR=0) Keep Input port (DDR=1, SSOE=0) (DDR=1) (DDR=1) (DDR=1, SSOE=1) 6, 7 Keep — I/O port 1 to 5 (DDR=0) (DDR=0) (DDR=0) Keep...
Page 922 Hardware Standby Software Bus- Program Name Mode Reset Mode Standby Mode Released Mode Execution Mode Keep 1, 2 Keep I/O port (SSOE = 0) 3, 4 (SSOE = 1) Keep (Address output)* (Address output)* (Address output)* (SSOE = 0) (Otherwise)* (Otherwise)* (SSOE = 1) Keep...
Page 923: Pin States At Reset
Pin States at Reset Modes 1 and 2: Figure D.1 is a timing diagram for the case in which RES goes low during an external memory access in mode 1 or 2. As soon as RES goes low, all ports are initialized to the input state.
Page 924 Modes 3 and 4: Figure D.2 is a timing diagram for the case in which RES goes low during an external memory access in mode 3 or 4. As soon as RES goes low, all ports are initialized to the input state.
Page 925 Access to external memory /φ Internal reset signal High impedance to A AS, RD (read) HWR, LWR (write) High impedance to D (write) High impedance I/O port, to CS Figure D.3 Reset during Memory Access (Mode 5) Modes 6 and 7: Figure D.4 is a timing diagram for the case in which RES goes low during an operation mode 6 or 7.
Page 926: Appendix E Timing Of Transition To And Recovery From Hardware Standby Mode
Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Timing of Transition to Hardware Standby Mode 1. To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low 10 system clock cycles before the STBY signal goes low, as shown below. RES must remain low until STBY goes low (minimum delay from STBY low to RES high: 0 ns).
Page 927: Appendix F Product Code Lineup
Appendix F Product Code Lineup Table F.1 H8/3062 Series Package Product Type Product Code Mark Code (Hitachi Package Code) H8/3062 On-chip HD64F3062F HD64F3062F 100-pin QFP (FP-100B) F-ZTAT flash HD64F3062TE HD64F3062TE 100-pin TQFP (TFP-100B) memory HD64F3062FP HD64F3062FP 100-pin QFP (FP-100A) H8/3062...
Page 928 Package Product Type Product Code Mark Code (Hitachi Package Code) H8/3064 On-chip HD64F3064F HD64F3064F 100-pin QFP (FP-100B) F-ZTAT flash HD64F3064TE HD64F3064TE 100-pin TQFP (TFP-100B) memory HD64F3064FP HD64F3064FP 100-pin QFP (FP-100A) HD64F3064VF HD64F3064VF 100-pin QFP (FP-100B) HD64F3064VTE HD64F3064VTE 100-pin TQFP (TFP-100B)
Page 929: Appendix G Package Dimensions
Appendix G Package Dimensions Figure G.1 shows the FP-100B package dimensions of the H8/3062 Series. Figure G.2 shows the TFP-100B package dimensions. Figure G.3 shows the FP-100A package dimensions. Unit: mm 16.0 ± 0.3 *0.22 ± 0.05 0.08 M 0.20 ± 0.04 0°...
Page 930 Unit: mm 16.0 ± 0.2 *0.22 ± 0.05 0.08 0.20 ± 0.04 0° – 8° 0.5 ± 0.1 0.10 Hitachi Code TFP-100B JEDEC — EIAJ Conforms *Dimension including the plating thickness Weight (reference value) 0.5 g Base material dimension Figure G.2 Package Dimensions (TFP-100B)
Page 931 24.8 ± 0.4 Unit: mm *0.32 ± 0.08 0.13 0.30 ± 0.06 0.58 0.83 0° – 10° 1.2 ± 0.2 0.15 Hitachi Code FP-100A JEDEC — EIAJ — *Dimension including the plating thickness Base material dimension Weight (reference value) 1.7 g...
Page 932: Appendix H Comparison Of H8/300H Series Product Specifications
Appendix H Comparison of H8/300H Series Product Specifications Differences between H8/3067 and H8/3062 Series, H8/3048 Series, H8/3007 and H8/3006, and H8/3002 H8/3067, H8/3062 H8/3048 Item Series Series H8/3006, H8/3007 H8/3002 Operating Mode 5 16 Mbyte ROM enabled 1 Mbyte mode...
Page 933 Yes (except products external output with on-chip flash function memory) Number of 3 channels (H8/3067) 2 channels 3 channels 2 channels channels 2 channels (H8/3062 Series) Smart card Supported on all Supported Supported on all interface channels on SCI0 channels...
Page 934 H8/3067, H8/3062 H8/3048 Item Series Series H8/3006, H8/3007 H8/3002 Conversion start External trigger/8-bit External External trigger/8-bit External converter trigger input timer compare match trigger timer compare match trigger Conversion 70/134 134/266 70/134 134/266 states φ pin φ/input port multiplexing φ output φ/input port multiplexing φ...
Page 935: Comparison Of Pin Functions Of 100-Pin Package Products (Fp-100B, Tfp-100B)
Comparison of Pin Functions of 100-Pin Package Products (FP-100B, TFP-100B) Table H.1 Pin Arrangement of Each Product (FP-100B, TFP-100B) On-chip-ROM Products ROMless Products H8/3006, H8/3067 Series H8/3062 Series H8/3048 Series H8/3042 Series H8/3007 H8/3002 /TMO /TMO /TMO TIOCA TIOCA TIOCA...
Page 936 On-chip-ROM Products ROMless Products H8/3006, H8/3067 Series H8/3062 Series H8/3048 Series H8/3042 Series H8/3007 H8/3002 /WAIT /WAIT /WAIT /WAIT /WAIT /WAIT...
Page 937 On-chip-ROM Products ROMless Products H8/3006, H8/3067 Series H8/3062 Series H8/3048 Series H8/3042 Series H8/3007 H8/3002 /BREQ /BREQ /BREQ /BREQ /BREQ /BREQ /BACK /BACK /BACK /BACK /BACK /BACK φ φ φ /φ /φ /φ STBY STBY STBY STBY STBY STBY EXTAL...
Page 938 On-chip-ROM Products ROMless Products H8/3006, H8/3067 Series H8/3062 Series H8/3048 Series H8/3042 Series H8/3007 H8/3002 /TCLKA PA TEND TEND TEND TEND TEND /TCLKA /TCLKA /TCLKA /TCLKA /TCLKA /TCLKB PA TEND TEND TEND TEND TEND /TCLKB /TCLKB /TCLKB /TCLKB /TCLKB TIOCA...
Page 939 Publication Date: 1st Edition, March 1998 3rd Edition, March 2000 Published by: Electronic Devices Sales & Marketing Group Semiconductor & Integrated Circuits Hitachi, Ltd. Edited by: Technical Documentation Group Hitachi Kodaira Semiconductor Co., Ltd. Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.

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Hitachi H8/3062 Hardware Manual

Section 1 Overview

Cpu

MCU Operating Modes

Exception Handling

Interrupt Controller

Bus Controller

I/O Ports

16-Bit Timer

8-Bit Timers

Section 10 Programmable Timing Pattern Controller (TPC)

Section 11 Watchdog Timer

Section 12 Serial Communication Interface

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