Hitachi H8S/2199 Hardware Manual page 483

Single-chip microcomputer

Table of Contents

Receive mode

[Clearing conditions]

1. When 0 is written by software (in cases other than setting condition 3)

2. When 0 is written in TRS after reading TRS = 1 (in case of setting condition 3)

3. When bus arbitration is lost after transmission is started in I

4. When the SW bit in DDCSWR changes from 1 to 0

Transmit mode

[Setting conditions]

1. When 1 is written by software (in cases other than clearing conditions 3)

2. When 1 is written in TRS after reading TRS = 0 (in case of clearing conditions 3)

3. When a 1 is received as the R/W bit of the first frame in I

Bit 3    Acknowledge Bit Judgement Selection (ACKE): Specifies whether the value of the

acknowledge bit returned from the receiving device when using the I

and continuous transfer is performed, or transfer is to be aborted and error handling, etc.,

performed if the acknowledge bit is 1. When the ACKE bit is 0, the value of the received

acknowledge bit is not indicated by the ACKB bit, which is always 0.

When the ACKE bit is 0, the TDRE, IRIC, and IRTR flags are set on completion of data

transmission, regardless of the value of the acknowledge bit. When the ACKE bit is 1, the TDRE,

IRIC, and IRTR flags are set on completion of data transmission when the acknowledge bit is 0,

and the IRIC flag alone is set on completion of data transmission when the acknowledge bit is 1.

Depending on the receiving device, the acknowledge bit may be significant, in indicating

completion of processing of the received data, for instance, or may be fixed at 1 and have no

significance.

The value of the acknowledge bit is ignored, and continuous transfer is performed

If the acknowledge bit is 1, continuous transfer is interrupted

C bus format master

C bus format slave mode

C bus format is to be ignored

Rev. 1.0, 02/00, page 475 of 1141

(Initial value)