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Register Description:
• Register configuration
Table 26.23 shows the register configuration of the CFG frequency division circuit.
Table 26.23 Register Configuration
Name
DVCFG control register
CFG frequency division
register 1
CFG frequency division
register 2
DVCFG mask period
register
DVCFG Control Register (CDVC)
Bit :
MCGin
Initial value :
R/W*
R/W :
Note: * Only 0 can be written
CDVC is an 8-bit register to control the capstan frequency division circuit.
It is initialized to H'60 by a reset, or in stand-by or module stop mode.
Bit 7 Mask CFG Flag (MCGin): MCGin is a flag to indicate occurrence of a frequency
division signal during the mask timer's mask period. To clear it by software, write 0 after reading
1. Also, setting has the highest priority in this flag. If a condition setting the flag and 0 write
occur simultaneously, the latter is invalid.
Bit 7
MCGin
Description
0
CFG is in normal operation
1
Shows that DVCFG was detected during masking (runaway detected)
Bit 6 Reserved: Cannot be modified and is always read as 1.
Abbrev.
CDVC
CDIVR1
CDIVR2
CTMR
7
6
—
CMK
0
1
—
R/W
Size
R/W
Byte
W
Byte
W
Byte
W
Byte
5
4
CMN
DVTRG
1
0
R
W
Initial Value
H'60
H'80
H'80
H'FF
3
2
CRF
CPS1
0
0
W
W
Rev. 1.0, 02/00, page 723 of 1141
Address
H'D09A
H'D09B
H'D09C
H'D09D
1
0
CPS0
0
0
W
W
(Initial value)
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