Hitachi SH7095 Manuals

Manuals and User Guides for Hitachi SH7095. We have 1 Hitachi SH7095 manual available for free PDF download: Hardware User Manual

Hitachi SH7095 Hardware User Manual (532 pages)

Brand: Hitachi | Category: Computer Hardware | Size: 4.17 MB

Table of Contents
3
Section 1 Overview and Pin Functions

12
- SH7095 Features
  12
  - Features of the SH7095
    12
- Block Diagram
  16
- Description of Pins
  17
  - Pin Arrangement
    17
  - Pin Functions
    18
Section 2 CPU

24
- Register Configuration
  24
  - General Registers
    24
  - Control Registers
    25
  - System Registers
    25
  - Initial Values of Registers
    26
- Data Formats
  26
  - Data Format in Registers
    27
  - Data Format in Memory
    27
  - Immediate Data Format
    28
- Instruction Features
  28
  - RISC-Type Instruction Set
    28
  - Addressing Modes
    30
  - Instruction Format
    34
- Instruction Set
  38
  - Instruction Set by Classification
    38
  - Operation Code Map
    51
- Processing States
  53
  - State Transitions
    53
  - Power-Down State
    55
Section 3 Operating Mode

58
Section 4 Exception Processing

64
Section 5 Interrupt Controller (INTC)

78
- Overview
  78
  - Features
    78
  - Block Diagram
    78
  - Pin Configuration
    80
  - Register Configuration
    80
- Interrupt Sources
  81
- Description of Registers
  87
- Interrupt Operation
  95
  - Interrupt Sequence
    95
  - Stack after Interrupt Exception Processing
    98
- Interrupt Response Time
  98
- Sampling of the IRL Pins (0-3)
  100
- Notes on Use
  101
Section 6 User Break Controller

106
- Overview
  106
  - Features
    106
  - Block Diagram
    107
  - Register Configuration
    108
- Register Descriptions
  109
  - Break Address Register a (BARA)
    109
  - Break Address Mask Register a (BAMRA)
    110
  - Break Bus Cycle Register a (BBRA)
    111
  - Break Address Register B (BARB)
    113
  - Break Address Mask Register B (BAMRB)
    113
  - Break Data Register B (BDRB)
    113
  - Break Data Mask Register B (BDMRB)
    114
  - Bus Break Register B (BBRB)
    115
  - Break Control Register (BRCR)
    116
- Operation
  119
  - Flow of the User Break Operation
    119
  - Break on Instruction Fetch Cycle
    120
  - Break on Data Access Cycle
    120
  - Break on External Bus Cycle
    121
  - Program Counter (PC) Values Saved
    121
  - Use Examples
    122
  - Notes on Use
    124
  - SH7000-Series Compatibility Mode
    125
Section 7 Bus State Controller (BSC)

128
- Overview
  128
  - Features
    128
  - Block Diagram
    129
  - Pin Configuration
    131
  - Register Configuration
    132
  - Address Map
    133
- Description of Registers
  135
- Access Size and Data Alignment
  147
  - Connections to Ordinary Devices
    147
  - Connections to Little Endian Devices
    149
- Accessing Ordinary Space
  150
  - Basic Timing
    150
  - Wait State Control
    154
- Synchronous DRAM Interface
  156
  - Synchronous DRAM Direct Connection
    156
  - Address Multiplex
    158
  - Burst Read
    159
  - Single Read
    162
  - Write
    163
  - Bank Active
    165
  - Refreshes
    171
  - Power-On Sequence
    174
  - Phase Shift by PLL
    176
- DRAM Interface
  179
  - DRAM Direct Connection
    179
  - Address Multiplex
    181
  - Basic Timing
    182
  - Wait State Control
    183
  - Burst Access
    185
  - Refresh Timing
    187
  - Power-On Sequence
    188
- Pseudo-SRAM Interface
  189
  - Pseudo-SRAM Direct Connection
    189
  - Basic Timing
    192
  - Wait State Control
    193
  - Burst Access
    195
  - Refresh
    196
  - Power-On Sequence
    198
- Burst ROM Interface
  198
- Waits between Access Cycles
  201
- Bus Arbitration
  202
  - Master Mode
    204
  - Slave Mode
    206
  - Partial-Share Master Mode
    207
  - External Bus Address Monitor
    210
  - Master and Slave Coordination
    210
- Other Topics
  211
  - Resets
    211
  - Access as Seen from the CPU or DMAC
    211
  - Emulator
    213
Section 8 Cache

214
- Introduction
  214
- Cache Control Register (CCR)
  215
- Address Space and the Cache
  216
- Cache Operation
  217
  - Cache Reads
    217
  - Writing
    220
  - Cache-Through Access
    221
  - The TAS Instruction
    222
  - Pseudo LRU and Cache Replacement
    222
  - Cache Initialization
    224
  - Associative Purges
    224
  - Data Array Access
    225
  - Address Array Access
    225
- Cache Use
  226
  - Initialization
    226
  - Purge of Specific Lines
    227
  - Cache Data Coherency
    228
  - Two-Way Cache Mode
    229
  - Usage Notes
    229
Section 9 Direct Memory Access Controller (DMAC)

232
- Overview
  232
  - Features
    232
  - Block Diagram
    233
  - Pin Configuration
    235
  - Register Configuration
    235
- Register Descriptions
  236
- Operation
  245
  - DMA Transfer Flow
    246
  - DMA Transfer Requests
    248
  - Channel Priority
    250
  - DMA Transfer Types
    252
  - Number of Bus Cycles
    260
  - DMA Transfer Request Acknowledge Signal Output Timing
    260
  - DREQ Pin Input Detection Timing
    271
  - DMA Transfer-End
    283
- Examples of Use
  285
  - DMA Transfer between On-Chip SCI and External Memory
    285
- Notes
  285
Section 10 Division Unit

288
- Overview
  288
  - Features
    288
  - Block Diagram
    288
  - Register Configuration
    289
- Description of Registers
  290
- Operation
  293
  - Bit/32 Bit Operations
    293
  - Handling of Overflows
    294
- Notes on Use
  294
  - Access
    294
  - Overflow Flag
    295
Section 11 16-Bit Free-Running Timer

296
- Overview
  296
  - Features
    296
  - Block Diagram
    297
  - Pin Configuration
    298
  - Register Configuration
    298
- Register Descriptions
  299
- CPU Interface
  306
- Operation
  309
  - FRC Count Timing
    309
  - Output Timing for Output Compare
    310
  - FRC Clear Timing
    310
  - Input Capture Input Timing
    311
  - Input Capture Flag (ICF) Set Timing
    312
  - Output Compare Flag (OCFA, OCFB) Set Timing
    312
  - Timer Overflow Flag (OVF) Set Timing
    313
- Interrupt Sources
  314
- Example of Using the FRT
  314
- Notes on Use
  314
Section 12 Watchdog Timer (WDT)

320
- Overview
  320
  - Features
    320
  - Block Diagram
    321
  - Pin Configuration
    321
  - Register Configuration
    322
- Register Descriptions
  322
- Operation
  327
- Notes on Use
  331
Section 13 Serial Communication Interface

334
- Overview
  334
  - Features
    334
  - Block Diagram
    335
  - Pin Configuration
    335
  - Register Configuration
    336
- Register Descriptions
  336
  - Receive Shift Register
    336
  - Receive Data Register
    336
  - Transmit Shift Register
    337
  - Transmit Data Register
    337
  - Serial Mode Register
    337
  - Serial Control Register
    340
  - Serial Status Register
    343
  - Bit Rate Register (BRR)
    347
- Operation
  352
  - Overview
    352
  - Operation in Asynchronous Mode
    355
  - Multiprocessor Communication
    365
  - Clocked Synchronous Operation
    373
- SCI Interrupt Sources and the DMAC
  382
- Notes on Use
  382
Section 14 Power-Down Modes

386
- Overview
  386
  - Power-Down Modes
    386
  - Register
    387
- Description of Register
  388
  - Standby Control Register (SBYCR)
    388
- Sleep Mode
  390
  - Transition to the Sleep Mode
    390
  - Canceling the Sleep Mode
    390
- Standby Mode
  390
  - Transition to the Standby Mode
    390
  - Canceling the Standby Mode
    391
  - Standby Mode Cancellation by NMI
    392
  - Clock Pause Function
    392
  - Notes on Standby Mode
    394
- Module Standby Function
  394
  - Transition to Module Standby Function
    394
  - Clearing the Module Standby Function
    394
Section 15 Electrical Characteristics

396
- Absolute Maximum Ratings
  396
- DC Characteristics
  397
- AC Characteristics
  399
  - Clock Timing
    399
  - Control Signal Timing
    403
  - Bus Timing
    409
  - DMAC Timing
    475
  - Free-Running Timer Timing
    476
  - Watchdog Timer Timing
    477
  - Serial Communications Interface Timing
    478
  - AC Characteristics Measurement Conditions
    479
Appendix A Pin States

480
Appendix B List of Register

482
- List of I/O Register
  482
- Register Chart
  490
Appendix C External Dimensions

532

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Hitachi SH7095 Manuals

Hitachi SH7095 Hardware User Manual (532 pages)

Table of Contents

Section 1 Overview and Pin Functions

Section 2 CPU

Section 3 Operating Mode

Section 4 Exception Processing

Section 5 Interrupt Controller (INTC)

Section 6 User Break Controller

Section 7 Bus State Controller (BSC)

Section 8 Cache

Section 9 Direct Memory Access Controller (DMAC)

Section 10 Division Unit

Section 11 16-Bit Free-Running Timer

Section 12 Watchdog Timer (WDT)

Section 13 Serial Communication Interface

Section 14 Power-Down Modes

Section 15 Electrical Characteristics

Appendix A Pin States

Appendix B List of Register

Appendix C External Dimensions

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