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TE bit
SCK1 output pin
SO1 output pin
Port input/output
Port
Figure 22.25 Asynchronous Transmission Using Internal Clock
TE bit
SCK1 output pin
SO1 output pin
Port input/output
Port
Note: * Initialized by software standby.
Figure 22.26 Synchronous Transmission Using Internal Clock
Rev. 1.0, 02/00, page 456 of 1141
Start of transmission
High output
Start
SCI TxD output
Start of transmission
Marking output
SCI TxD output
Transition
End of
transmission
to standby
Stop
End of
Transition
transmission
to standby
Last TxD bit held
Exit from
standby
Port input/output
Port input/output
High output
SCI TxD
Port
output
Exit from
standby
Port input/output
Port input/output
High output*
SCI TxD
Port
output
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