Hitachi H8S/2199 Hardware Manual page 1078

Single-chip microcomputer
Table of Contents

Advertisement

H'D212: OSD Format Register DFORM: OSD
15
:
Bit
TVM2
:
Initial value
0
R/W
:
R/W
TV format select bits
Bit 15
TVM2
0
0
0
0
1
1
1
1
Notes: 1. Only 0 can be written to clear the flag.
2. The 4fsc and 2fsc frequencies for SECAM do not conform to the SECAM TV format
specifications.
Rev. 1.0, 02/00, page 1076 of 1141
14
13
TVM1
TVM0
FSCIN
0
0
R/W
R/W
R/W
4/2fsc external input select bit
4/2fsc oscillator uses a crystal oscillator
0
1
4/2fsc uses a dedicated amplifier circuit for external clock signal input
4/2fsc input select bit
4fsc input is selected
0
2fsc input is selected
1
Bit 14
Bit 13
Bit 12
TVM1
TVM0
FSCIN
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
12
11
10
FSCEXT
0
0
0
R/W
OSDV interrupt flag
0
1
OSDV interrupt enable bit
0
The OSDV interrupt is disabled
1
The OSDV interrupt is enabled
(Initial value)
TV Format
0
M/NTSC
1
17.734475
0
(17.734470)
4.43-NTSC
1
0
M/PAL
(14.302444)
1
0/1
Must not be specified
0
14.328225
N/PAL
(14.28244)
1
0/1
Must not be specified
0
B,G,H/PAL
(17.734476)
I/PAL
1
D,K/PAL
2
0
B,G,H/SECAM*
(17.734470)
L/SECAM
1
D,K,K1/SECAM
9
8
OSDVE
OSDVF
0
0
1
R/W
R/(W)*
[Clearing condition]
When 0 is written after reading 1
[Setting condition]
When OSD detects the Vsync signal
(Initial value)
Description
4fsc (MHz)
2fsc (MHz)
14.31818
7.15909
8.867235
(8.867238)
14.302446
7.15122298
7.1641125
17.734475
8.867235
(8.867238)
17.734475
8.867235
(8.867238)
(Initial value)
(Initial value)

Advertisement

Table of Contents
loading

Table of Contents