Rts Instruction - Hitachi H8S/2199 Hardware Manual

2. JMP Instruction (Memory indirect)
When the trap address is the next instruction to the JMP instruction and the addressing mode is
memory indirect, transition is made to the address trap interrupt after prefetching the
instruction at the branch. The address to be stacked is 02E4.
JMP
instruc-
tion
pre-fetch
φ
Address bus
0294
Interrupt
request
signal
Note: * Trap setting address
The underlines address is the one to be actually stacked.
25.3.7

RTS Instruction

When the trap address is the next instruction to the RTS instruction, transition is made to the
address trap interrupt after reading the CCR and PC from the stack and prefetching the instruction
at the return location. The address to be stacked is 0298.
RTS
instruc-
tion
pre-fetch
φ
Address bus
02AC
Break interrupt
request signal
Note: * Trap setting address
The underlines address is the one to be actually stacked.
NOP Internal
Data
instruc-
fetch
tion
pre-fetch
0296 006C 006E
JMP execution
Figure 25.14 JMP Instruction (Memory Indirect)
Internal
NOP Stack
opera-
instruc-
saving
tion
tion
pre-fetch
02AE SP SP+2 SP
RTS execution
Figure 25.15 RTS Instruction
NOP
Start of
instruc-
opera-
exception
tion tion
handling
pre-fetch
006C 02E4 02E6
NOP
Start of
instruc-
exception
tion
handling
pre-fetch
0298 029A
006C H'02E4
:
0294 JMP @@H'6C:8
0296 NOP
*
0298 NOP
:
02E4 NOP
02E6 NOP
(@ER0 = H'02C8)
0296 BSR SUB
0298 NOP
029A NOP
*
Rev. 1.0, 02/00, page 545 of 1141
:
:
: :
02AC RTS
02AE NOP