Register Descriptions; Timer L Mode Register (Lmr) - Hitachi H8S/2199 Hardware Manual

14.2

Register Descriptions

14.2.1

Timer L Mode Register (LMR)

Bit :
Initial value :
R/W :
R /(W)*
Note: * Only 0 can be written to clear the flag.
The timer L mode register A (LMR) is an 8-bit read/write register which works to control the
interrupts, to select between up-counting and down-counting and to select the clock source. When
reset, the LMR is initialized to H'30.
Bit 7    Timer L Interrupt Requesting Flag (LMIF): This is the Timer L interrupt requesting
flag. It indicates occurrence of overflow or underflow of the LTC or occurrence of compare
match clear.
Bit 7
LMIF Description
0 [Clearing conditions]
When 0 is written after reading 1
1 [Setting conditions]
When the LTC overflows, underflows or when compare match clear has occurred
Bit 6    Enabling Interrupt of the Timer L (LMIE): This bit works to permit/prohibit
occurrence of interrupt of timer L when the LTC overflows, underflows or when compare match
clear has occurred.
Bit 6
LMIE Description
0 Prohibits occurrence of interrupt of Timer L
1 Permits occurrence of interrupt of Timer L
Bits 5 and 4    Reserved: These bits cannot be modified and are always read as 1.
Bit 3    Up-Count/Down-Count Control (LMR3): This bit is for selection if timer L is to be
controlled to the up-counting function or down-counting function.
Rev. 1.0, 02/00, page 282 of 1141
7 6
LMIF LMIE
0 0
R/W
5 4 3
LMR3
— —
1 1 0
— —
R/W
2 1
LMR2 LMR1 LMR0
0 0
R/W R/W
(Initial value)
(Initial value)
0
0
R/W