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7.6.3
Error Protection
In error protection, an error is detected when MCU runaway occurs during flash memory
programming/erasing, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is aborted. Aborting the program/erase operation
prevents damage to the flash memory due to overprogramming or overerasing.
If the MCU malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in
FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2
settings are retained, but program mode or erase mode is aborted at the point at which the error
occurred. Program mode or erase mode cannot be re-entered by re-setting the P or E bit.
However, PV1, PV2, EV1 and EV2 bit setting is enabled, and a transition can be made to verify
mode.
FLER bit setting conditions are as follows:
• When flash memory is read during programming/erasing (including a vector read or instruction
fetch)
• Immediately after exception handling (excluding a reset) during programming/erasing
• When a SLEEP instruction (including standby) is executed during programming/erasing
Error protection is released only by a reset and in hardware standby mode.
Figure 7.14 shows the flash memory state transition diagram.
Program mode
Erase mode
PR ER FLER = 0
Error occurrence
Error protection mode
RD VF
FLER = 1
Power-down mode
Power-down mode release
[Legend]
RD
: Memory read possible
VF
: Verify-read possible
PR
: Programming possible
ER
: Erasing possible
Figure 7.14 Flash Memory State Transitions
(hardware protection)
= 0
= 0
Error protection
mode (power-down mode)
FLMCR1, FLMCR2 (except FLER bit), EBR1, EBR2
initialization state
: Memory read impossible
: Verify-read impossible
: Programming impossible
: Erasing impossible
Reset
P
FLER = 0
FLMCR1, FLMCR2,
EBR1, EBR2 initialization
state
FLER = 1
Rev. 1.0, 02/00, page 155 of 1141
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