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V
CC
SCL
SCL
in
out
SDA
SDA
in
out
(Master)
This chip
Figure 23.2 I
23.1.3
Pin Configuration
Table 23.1 summarizes the input/output pins used by the I
2
Table 23.1 I
C Bus Interface Pins
Channel Name
0
Serial clock pin
Serial data pin
Formatless serial clock pin
1
Serial clock pin
Serial data pin
Note:
*
In this section, channel numbers in the abbreviated register names are omitted; SCL0
and SCL1 are collectively referred to as SCL, and SDA0 and SDA1 as SDA.
SCL
in
out
SDA
in
out
(Slave 1)
2
C Bus Interface Connections (Example: This Chip as Master)
Abbrev.* I/O
SCL0
SDA0
SYNCI
SCL1
SDA1
SCL
in
out
SDA
in
out
(Slave 2)
2
C bus interface.
Function
Input/output IIC0 serial clock input/output
Input/output IIC0 serial data input/output
Input
IIC0 formatless serial clock input
Input/output IIC1 serial clock input/output
Input/output IIC1 serial data input/output
Rev. 1.0, 02/00, page 461 of 1141
SCL
SDA
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