Hitachi H8S/2199 Hardware Manual page 709

Single-chip microcomputer
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VD
REF30P
HSW
Capstan phase control
ASM mode, PB mode: REF30X-PB-CTL
REF30X
CTL
16bit
UP/DOWN
counter
DVCFG2
CREF
Notes: 1.
Ta is the interval calculated from RDCR3.
2.
Tb is the interval in which switchover is
performed from ASM mode to REC mode.
3.
Tx is the cycle in which the REF30X period
is shortened due to the change of XDR.
4.
With CREF and DVCFG2 phase alignment,
the frequency need not be 25 Hz or 30 Hz.
Figure 26.51 Example of CTLM Switchover Timing
(When Phase Control Is Performed by CREF and DVCFG2 in Rec Mode)
The X-value is updated by REF30P. Modification of XDR must be performed
before REF30P in the cycle in which the X-value is changed.
X-value (XDR) is
rewritten in this
cycle
X value
PB-CTL
Ta
φ/5
φ/4
0 pulse
1 pulse
CDIVR2
Register write
X-value after
change
Tx
REC-CTL
Tb
φ/4
RCDR1
RCDR3
UDF
0 pulse
ASM-REC
switchover
Capstan phase control
REC mode : CREF30P-DVCFG2
Rev. 1.0, 02/00, page 703 of 1141
RCDR1
RCDR2
1 pulse
Latch
Preset

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