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26.6.4
Register Description
Specified DFG Speed Preset Data Register (DFPR)
15
Bit :
DFPR15
Initial value :
R/W :
W
Bit :
DFPR7
Initial value :
R/W :
W
The DFG speed preset data is set in DFPR. When data is written, the 16-bit preset data is sent to
the preset circuit. The preset data can be calculated from the following equation by using H'8000*
as the reference value.
Specified DFG speed preset data = H ' 8000 − (
φ s:
Servo clock frequency (fosc/2) in Hz
DFG frequency: In Hz
Constant 2 is the presetting interval (see Figure 26.28).
φ s/n
Clock source of the selected counter
DFPR is a 16-bit write-only register. Only a word access is valid. If a byte access is attempted,
correct operation is not guaranteed. DFPR cannot be read. If a read is attempted, an
undetermined value is read. DFPR is initialized to H'0000 by a reset, and in standby mode and
module stop mode.
Note: The preset data value is calculated so that the counter will reach H'8000 when the error is
zero. When the counter value is latched as error data in the DFG speed error data register
(DFER), however, it is converted to a value referenced to H'0000.
14
13
DFPR14
DFPR13
0
0
W
W
7
6
DFPR6
DFPR5
0
0
W
W
12
11
DFPR12
DFPR11
0
0
W
5
4
DFPR4
DFPR3
0
0
W
φs / n
DFG frequency
10
DFPR10
DFPR9
0
0
W
W
3
2
DFPR2
DFPR1
0
0
W
W
− 2)
Rev. 1.0, 02/00, page 621 of 1141
9
8
DFPR8
0
0
W
W
1
0
DFPR0
0
0
W
W
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