Noise Detection Level Register (Ndetr) - Hitachi H8S/2199 Hardware Manual

Single-chip microcomputer

Table of Contents

Noise Detection Level Register (NDETR)

Initial value :

The NDETR is an 8-bit write-only register for specifying the noise detection level. The set value

must be 1/4 of the actual noise detection level. The noise detection window signal is set to 1 at a

falling edge of the OSCH signal, and reset to 0 after the time specified by the HHK period setting

bits has passed. The OSCH signal falls about 5 µs after a rising edge of the SEPH signal.

When the noise detection counter value matches the specified noise detection level, the noise

detection interrupt request flag is set to 1. When reset, the NDETR is initialized to H'00. The

NDETR is assigned to the same address as the NDETC.

Figure 27.13 shows the timing for noise detection.

H complement and

mask counter

Noise detection window

Figure 27.13 Noise Detection Window Setting and Noise Counting Timing

Rev. 1.0, 02/00, page 780 of 1141

Cleared to 0 by CPU

Noise counter