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H'D241: Sync Separation Control Register SEPCR: Sync Separator
7
:
Bit
AFCVIE
Initial value
:
0
R/W
:
R/W
External Vsync interrupt flag
External Vsync interrupt enable
The external Vsync interrupt is disabled
0
The external Vsync interrupt is enabled
1
Note: *Only 0 can be written to clear the flag
Rev. 1.0, 02/00, page 1084 of 1141
6
5
AFCVIF
VCKSL
0
0
R/(W)*
R/W
V complement function control
V complement and mask counter clock source select
0
Double the frequency of the horizontal sync signal (AFCH signal) for the AFC (Initial value)
1
Double the frequency of the horizontal sync signal (OSCH signal) for the
H complement and mask counter
0
[Clearing condition]
1 is read, then 0 is written
1
[Setting condition]
The V complement and mask counter detects the external Vsync signal (AFCV signal)
4
3
VCMPON
HCKSEL
HHKON
0
0
R/W
R/W
HHK forcibly turned on
0
1
Internal csync generator clock source select
0
4/2 fsc clock
1
AFC reference clock
The V complement function is disabled
0
The V complement function is enabled
1
(Initial value)
2
1
—
0
0
R/W
R/W
Field detection flag
0
Even field
Odd field
1
The HHK is not operated when complementary
pulses are interpolated three successive times
The HHK is forcibly operated when complementary
pulses are interpolated three successive times
(Initial value)
(Initial value)
0
FLD
0
R
(Initial value)
(Initial value)
(Initial value)
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