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26.1.2
Block Diagram
Figure 26.1 shows a block diagram of the servo circuits.
PPG0 to 7/
(P70 to 77)
RP0 to 7/
(P60 to 67,
P74 to 77)
EXTTRG(P86)
COMP(P85)
C.ROTARY(P83)
H.Amp SW(P84)
AUDIOFF
VIDEOFF
DPG(P87)
DFG
CFG
SV1(P30)
SV2(P31)
EXCTL(P82)
CTL Amp
CTL
CTL
EXCAP(P81)
Rev. 1.0, 02/00, page 556 of 1141
PPG0 to 7/
(P70 to 77)
RP0 to 7/
(P60 to 67,
P74 to 77)
Csync
4-head
special
playback
controller
Additional
Vpulse
V pulse
generator
Head-switch
timing
generator
Noise
Det.
Speed
error
detector
DRM
PWM
PWM
Gain up.
CAP
PWM
PWM
Gain up.
Frequency
divider
(
)
(
)
Frequency
)
divider
CTLFB
- +
Gain control
- +
by register
setting
+
Head
-
Head
Figure 26.1 Block Diagram of Servo Circuits
Sync
separator
VD
REC:ON
XE:ON
ADTRIG
(HSW)
Phase
Ep
Digital
error
detector
Es
+
Digital
filter
+
+
Digital
filter
+
DVCFG
Speed
Es
error
detector
DVCFG2
REC
Ep
Phase
Digital
error
detector
PB.ASM
(NTSC)
PB.
REC
ASM
(PAL)
REF30X
PB.CTL
VISS
circuit
DutyI/O
(Duty deter-
minator)
REC-CTL
System
clock
Capstan
Res
Drum system
system
reference
reference
signal
signal
filter
converter
Timer X1
Timer L
Timer R
filter
X-value
adjustment
REC-CTL
generator
(Assemble
recording)
A/D
AN pins
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