Hitachi H8S/2199 Hardware Manual page 651

Bit 2    Capstan Phase System Filter Computation Automatic Start Bit (CPCNT): Enables the
filter computation of the phase system if an underflow occurred in the capstan lock counter.
Bit 2
CPCNT Description
0 Disables the filter computation by detection of the capstan lock.
1 Enables the filter computation of the phase system when capstan lock is
detected.
Bits 1 and 0    Capstan Lock Counter Setting Bits (CFRCS1, CFRCS0): Sets the number of
times to detect capstan locks (DVCFG has been detected in the rage set by the lock range data
register). The capstan lock flag is set when the specified number of capstan lock is detected. If the
DVCFG signal is detected outside the lock range after data is written in CFRCS1 and CFRCS0,
the data will be stored in the lock counter.
Note: If CFRCS1 or CFRCS0 is read-accessed, the counter value is read out. If bit 3 (capstan
lock flag) is 1 and the capstan lock counter's value is 3, it indicates that the capstan speed
system is locked. The capstan lock counter stops until lock is released after underflow.
Bit 1 Bit 0
CFRCS1 CFRCS0
0 0
1
1 0
1
Description
Underflow occurs after lock was detected once
Underflow occurs after lock was detected twice
Underflow occurs after lock was detected three times
Underflow occurs after lock was detected four times
Rev. 1.0, 02/00, page 645 of 1141
(Initial value)
(Initial value)