Hitachi H8S/2199 Hardware Manual page 761

Servo Interrupt Request Register 2 (SIRQR2)
Bit :
Initial value :
R/W :
Note: * Only 0 can be written to clear the flag.
SIRQR2 is an 8-bit read/write register that indicates interrupt request in the servo section. If the
interrupt request has occurred, the corresponding bit is set to 1.
Writing 0 after reading 1 is allowed; no other writing is allowed. It is initialized to H'FC by a
reset, or in stand-by or module stop mode.
Bits 7 to 2Reserved: Cannot be modified and are always read as 1.
Bit 1    Vertical Sync Signal Interrupt Request Bit (IRRSNC)
Bit 1
IRRSNC Description
0 No interrupt request from the sync signal detector (VD, noise)
1 Interrupt requested from the sync signal detector (VD, noise)
Bit 0    CTL Signal Interrupt Request Bit (IRRCTL)
Bit 0
IRRCTL Description
0 No interrupt request from CTL
1 Interrupt requested from CTL
7 6
— —
1 1
— —
5 4
— —
1 1
— —
3 2
IRRSNC
— —
1 1
— — R/(W)*
Rev. 1.0, 02/00, page 755 of 1141
1 0
IRRCTL
0 0
R/(W)*
(Initial value)
(Initial value)