26.13.5 Register Description - Hitachi H8S/2199 Hardware Manual

26.13.5 Register Description

CTL Control Register (CTCR)
Bit :
Initial value :
R/W :
CTCR is an 8-bit read/write register that controls PB-CTL rewrite and sets the slow mode. When
CTL pulse cannot be detected with the input amplifier gain set at the CTL gain control register
(CTLGR) in PB-CTL circuit, bit 1 (UNCTL) of CTCR is set to 1. It is automatically cleared to 0
when CTL pulse is detected.
Bit 1 is read-only, and the rest are write-only. If a read is attempted to a write-only bit, an
undetermined value is read out.
CTCR is initialized to H'30 by a reset, and in standby and module stop mode.
Bit 7    NTSC/PAL Select (NT/PL): Selects the period of the rewrite circuit.
Bit 7
NT/PL Description
0 NTSC mode (frame rate: 30 Hz)
1 PAL mode (frame rate: 25 Hz)
Bits 6 to 4    Frequency Select (FSLA, FSLB, FSLC); These bits select the operating frequency
of the CTL write circuit. They should be set according to fOSC.
Bit 1 Bit 0
FSLC FSLB
0 0
1
1 *
Note: * Don't care.
7 6
NT/PL FSLC FSLB
0 0
W W
Bit 0
FSLA
0
1
0
1
*
5 4 3
FSLA CCS
1 1 0
W W W
Description
Reserved (do not use this setting)
Reserved (do not use this setting)
fosc = 8 MHz
fosc = 10 MHz
Reserved (do not use this setting)
2 1
LCTL UNCTL
0 0
W R
Rev. 1.0, 02/00, page 687 of 1141
0
SLWM
0
W
(Initial value)
(Initial value)