Hitachi H8S/2199 Hardware Manual page 1021

H'D096: Reference Frequency Mode Register RFM: Reference Signal Generator
Bit : 7
RCS
0
Initial value :
R/W : W
Mode select bit
0 Manual mode
1 Auto mode
Clock source select bit
0 φs/2
(Initial value)
1 φs/4
H'D097: Reference Frequency Mode Register 2 RFM2: Reference Signal Generator
Bit :
7
TBC
Initial value :
1
R/W :
R/W
TBC select bit
0 Reference signal is generated by VD
signal
1 Reference signal is generated by free-running
counter
6 5 4
VNA CVS REX
0 0 0
W W W
External signal synchronization select bit
0 VD signal or free-run
1 External signal sync
Manual select bit
0 VD sync (Initial value)
1 Free-run
(Initial value)
6 5
— —
1 1
— —
3 2
CRD OD/EV
0 0
W W
VideoFF counter set
0 VideoFF signal turns counter set off
1 VideoFF signal turns counter set on
ODD/EVEN edge switchoverselect bit
0 Generated at field signal rising (even)
1 Generated at field signal rising (odd)
DVCFG2 synchronization select bit
0 At mode switching (initial value)
1 DVCFG2 signal synchronized
(Initial value)
4 3
— — —
1 1
— — —
1 0
VST VEG
0 0
W W
VideoFF edge select bit
0 Set at VideoFF signal rising
1 Set at VideoFF signal falling
2 1 0
— FDS
1 1 0
— R/W
Field select bit
0 Generated by selected ODD or EVEN VD
signal
1 Generated by VD signal within mode transition
phase error of 90˚
Rev. 1.0, 02/00, page 1019 of 1141
(Initial value)
(Initial value)
(Initial value)
(Initial value)