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27.3.2
Vsync Separation
The Hsync separator separates the Vsync signal from the Csync signal by using the digital V
separation counter, which is an 8-bit up-/down-counter, and the VVTHR register, which holds the
threshold value. The digital V separation counter increments the count when the Csync signal is
high, and decrements the count when the Csync is low. When the count reaches the VVTHR value
while the count is incremented, the SEPV signal is set to 1 and the counter stops until the Csync
signal goes low. When the Csync signal goes low, the counter starts to decrement the count. When
the count reaches H'00, the SEPV signal is reset to 0 and the counter stops until the Csync signal
goes high. Set the VVTHR value so that the SEPV signal goes high 1/2 or more after the Vsync
start position to correctly separate the Vsync signal against the signal disturbance in a weak field
or the motor skew during video tape playback.
The obtained SEPV signal is sent to the V complement and mask counter. The V complement and
mask counter is reset to 0 when the SEPV signal is input, and increments the count at twice the
frequency (2 × fh) of the horizontal sync signal for the Vsync signal (SEPV signal) cycle period.
This counter masks the reset signal (SEPV) for about 85% (NTSC) or 72% (PAL) of the period
from a reset to the next reset; even if a SEPV signal generated by noise is input to the counter
during this period, the counter is not reset. If no SEPV signal is input after the mask period ends,
the mask is left cleared; the next SEPV signal input resets the counter, and the counter is
synchronized with the SEPV signal. When the counter is reset by the SEPV signal, the external
Vsync detection signal (AFCV) is generated and the external Vsync interrupt flag is set to 1.
The Vsync separation function includes the digital LPF function and the Vsync complement
function, which reduce the chance of the Vsync detection being delayed or missed due to the
Vsync disturbance in a weak field.
(1) Digital LPF Function
This function logically ORs the Csync (Vsync) signal and the SEPH signal separated by the
digital H counter to mask the noise component due to loss of a Vsync pulse. The digital V
separation counter increment the count when the resultant signal is input. Loss of a Vsync
pulse in a weak field causes SEPV signal detection to be delayed or missed, which will result
in incorrect detection of fields or lines. To enable this function, set the DLPFON bit (bit 2) of
the SEPIMR to 1. For the timing, refer to figure 27.9.
(2) Vsync Complement Function
This function makes the V complement and mask counter increment the count at a clock
having twice the frequency (2 × fh) of the horizontal sync signal (AFCH), and generates the
AFCV signal (Vsync signal) from the count if a Vsync pulse is lost.
The count value is decoded in different ways depending on the TV format. The source of the
clock for the V complement and mask counter can be switched between the AFC or the H
complement and mask counter. This function can reduce the chance of the SEPV signal
detection being delayed and missed in a weak field. To enable this function, set the VCMPON
bit (bit 4) of the SEPCR to 1. For the timing, refer to figure 27.10.
Rev. 1.0, 02/00, page 790 of 1141
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