Hitachi H8S/2199 Hardware Manual page 611

Single-chip microcomputer
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FIFO Timer Capture Register (FTCTR)
15
Bit :
FTCTR15
Initial value :
R/W :
R
Bit :
FTCTR7
Initial value :
R/W :
R
FTCRT is a register to display the count of the 16-bit timer counter.
FTCRT is an 16-bit read-only register. It captures the counter value when the VD signal is
detected in PB mode. Only a word access is accepted. If a byte access is attempted, correct
operation is not guaranteed. It is initialized to H'0000 by a reset or in stand-by mode.
Note: The same address is assigned to the FTCTR and the FIFO timing pattern register 1
(FTPRA). Accordingly, if a write is attempted, the value is written in FTPRA.
DFG Reference Count Register (DFCTR)
Bit :
Initial value :
R/W :
Note : * Don't care
DFCTR is a register to count DFG pulses.
DFCTR is an 8-bit read-only register. Bits 7 to 5 are reserved; they cannot be modified and are
always read as 1. It is initialized to H'E0 by a reset or in stand-by mode.
Note: The same address is assigned to the DFCTR and the DFG reference register 1 (DFCRA).
Accordingly, if a write is attempted, the value is written in DFCRA.
Bits 4 to 0—DFG Pulse Count Bits (DFCTR4 to DFCTR0): These bits count DFG pulses.
14
13
FTCTR14 FTCTR13
0
0
R
7
6
FTCTR6
FTCTR5
0
0
R
7
6
1
1
12
FTCTR12 FTCTR11 FTCTR10 FTCTR9
0
0
R
R
5
4
FTCTR4
FTCTR3
0
0
R
R
5
4
DFCTR4
DFCTR3
1
*
R
11
10
0
0
R
R
3
2
FTCTR2
FTCTR1
0
0
R
R
3
2
DFCTR2 DFCTR1
*
*
R
R
Rev. 1.0, 02/00, page 605 of 1141
9
8
FTCTR8
0
0
R
R
1
0
FTCTR0
0
0
R
R
1
0
DFCTR0
*
*
R
R

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