Hitachi H8S/2199 Hardware Manual page 520

Single-chip microcomputer

Table of Contents

Table 23.7 I

C Bus Timing (with Maximum Influence of t

Notes: 1. Does not meet the I

following is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the

rise and fall times by means of a pull-up resistor and capacitive load; (c) reduce the

transfer rate; (d) select slave devices whose input timing permits this output timing.

The values in the above table will vary depending on the settings of the IICX bit and bits

CKS0 to CKS2. Depending on the frequency it may not be possible to achieve the

maximum transfer rate; therefore, whether or not the I

met must be determined in accordance with the actual setting conditions.

2. Value when the IICX bit is set to 1. When the IICX bit is cleared to 0, the value is (t

3. Calculated using the I

speed mode: 1300 ns min.).

Rev. 1.0, 02/00, page 512 of 1141

C bus interface specification. Remedial action such as the

C bus specification values (standard mode: 4700 ns min.; high-

Time Indication (at Maximum Transfer Rate) [ns]

Specification

φ φ φ φ = 8 MHz

C bus interface specifications are

φ φ φ φ = 10 MHz