Drum Speed Error Detector; Overview; Block Diagram - Hitachi H8S/2199 Hardware Manual

Single-chip microcomputer

Table of Contents

Drum Speed Error Detector

Drum speed error control holds the drum at a constant revolution speed, by measuring the period

of the DFG signal. A digital counter detects the speed error against a preset value. The speed

error data is processed and added to phase error data in a digital filter. This filter controls a pulse-

width modulated (PWM) output, which controls the revolution speed and phase of the drum.

The DFG input signal is reshaped into a square wave by a reshaping circuit, and sent to the speed

error detector as the DFG signal.

The speed error detector uses the system clock to measure the period of the DFG signal, and

detects the error against a preset data value. The preset data is the value that results from

measuring the DFG signal period with the clock signal when the drum motor is running at the

correct speed.

The error detector operates by latching a counter value when it detects an edge of the DFG signal.

The latched count provides 16 bits of speed error data for the digital filter to operate on. The

digital filter processes and adds the speed error data to phase error data from the drum phase

control system, then sends the result to the PWM as drum error data.

Figure 26.27 shows a block diagram of the drum speed error detector.

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