Hitachi H8S/2199 Hardware Manual page 781

Single-chip microcomputer

Table of Contents

Bit 0    Field Detection Flag (FLD): Indicates the field determined by the status of the field

detection window signal generated by the AFC when the external Vsync signal (AFCV signal)

rises. This flag is invalid when the internally generated Hsync signal is selected as the AFC

reference Hsync signal. For the timing, refer to section 27.2.6, Field Detection Window Register

Digital V separation

AFC frequency-

dividing counter

When V complement

function is not operating:

Field detection

window signal

When V complement

function is operating:

Field detection

window signal

V complement and

mask counter clock

: Field detection window register value

Rev. 1.0, 02/00, page 776 of 1141

Odd field timing

Figure 27.11 Field Detection Timing

(Initial value)

Even field timing