Hitachi H8S/2199 Hardware Manual page 819

The data slicer initialization and operation for one specification example are shown in figure 28.9.
Contents of slice line setting registers
Register No.
Enable
1
2
3
4
Even field
Odd field
Note: Data slice operation is not performed for line a, because the enable bit = 0. Further, when the same line
is specified within the same field, erroneous operation results; do not specify the same line in the same
field. For details on the external Vsync interrupt, refer to section 27.2.2, Sync Separation Control
Register (SEPCR).
Figure 28.9 Example of Slice Line Specification and Operation (1)
Slice Line Setting Register
Field Line
1 Even
Line c
1 Odd
Line b
1 Even
Line d
0 Odd
Line a
Start
An external Vsync interrupt
occurs
Set the slice (even and odd)
field mode registers
Set the slice line setting
registers 1 to 4
(except the enable bits)
Set the enable bits of
the slice line setting
registers 1 through 3 to 1
An external Vsync interrupt
occurs
Execute slicing for line c
Execute slicing for line d
An external Vsync interrupt
occurs
Execute slicing for line b
d > c
b > a
Reset the slice enable bit
Reset the slice enable bit
Generate an even field slice completion
interrupt
Reset the slice enable bit
Generate an odd field slice completion
interrupt
Rev. 1.0, 02/00, page 815 of 1141
Initialize the data slicer