Hitachi H8S/2199 Hardware Manual page 1064

H'D14A: Serial Control Register SCR1: SCI1
Bit :
Initial value :
R/W :
Receive enable bit
0
1
Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states.
2. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial
clock input is detected in synchronous mode.
SMR setting must be performed to decide the reception format before setting the RE bit to 1.
Transmit enable bit
0 Transmission is disabled
1 Transmission is enabled
Notes: 1. The TDRE flag in SSR is fixed at 1.
2. In this state, serial transmission is started when transmit data is written to TDR and TDRE flag in SSR
is cleared to 0.
SMR setting must be performed to decide the transmission format before setting the TE bit to 1.
Receive interrupt enable bit
0 Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request is disabled*
1 Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request is enabled
Note: * RXI and ERI interrupt request cancellation can be performed by reading 1 from the RDRF, FER, PER, or ORER flag,
then clearing the flag to 0, or clearing the RIE bit to 0.
Transmit interrupt enable bit
0 Transmit-data-empty interrupt (TXI) request is disabled*
1 Transmit-data-empty interrupt (TXI) request is enabled
Note: * TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then clearing it to 0,
or clearing the TIE bit to 0.
Rev. 1.0, 02/00, page 1062 of 1141
7 6 5
TIE
RIE TE
0 0 0
R/W R/W R/W
Clock enable bits
CKE1 CKE0
0 0
1
1 0
1
Notes: 1. Initial value
2. Outputs a clock of the same frequency as the bit rate.
3. Inputs a clock with a frequency 16 times the bit rate.
Transmit end interrupt enable bit
0 Transmit-end interrupt (TEI) request is disabled*
1 Transmit-end interrupt (TEI) request is enabled*
Note: * TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing it
to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0.
Multiprocessor interrupt enable bit
Multiprocessor interrupts are disabled (normal reception performed)
0
[Clearing conditions]
(1) When the MPIE bit is cleared to 0
(2) When data with MPB = 1 is received
Multiprocessor interrupt are enabled*
1
Receive interrupt (RXI) requests, receive-error interrupt (ERI) requests, and setting of the RDRF,
FER, and ORER flags in SSR1 are disabled until data with the multiprocessor bit set to 1 is received.
Note: * When receive data including MPB = 0 is received, receive data transfer from RSR to RDR, receive error detection, and
setting of the RDRF, FER, and ORER flags in SSR, is not performed. When receive data with MPB = 1 is received,
the MPB bit in SSR is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts
(when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag setting is enabled.
*1
Reception is disabled
*2
Reception is enabled
*1
*2
4 3 2
RE MPIE TEIE
0 0 0
R/W R/W R/W
Clock select
Asynchronous mode Internal clock/SCK pin functions as I/O port
Clock synchronous mode Internal clock/SCK pin functions as synchronous clock output
Asynchronous mode Internal clock/SCK pin functions as clock output
Clock synchronous mode
Internal clock/SCK pin functions as synchronous clock output
Asynchronous mode External clock/SCK pin functions as clock input
Clock synchronous mode External clock/SCK pin functions as synchronous clock input
Asynchronous mode External clock/SCK pin functions as clock input
Clock synchronous mode External clock/SCK pin functions as synchronous clock input
(Initial value)
(Initial value)
(Initial value)
1 0
CKE1 CKE0
0 0
R/W R/W
*1
(Initial value)
*3
*3
(Initial value)
(Initial value)
(Initial value)
*1
*2