Hitachi H8S/2199 Hardware Manual page 728

26.14.3 CFG Frequency Divider
Block Diagram: Figure 26.65 shows a block diagram of the 7-bit CFG frequency divider and its
mask timer.
CDVC
CRF
Edge
CFG
select
↑, ↑↓
PB(ASM)→REC
φs/1024
φs/512
φs/256
φs/128
DVTRG
W
Rev. 1.0, 02/00, page 722 of 1141
W
W
CDIVR(7 bits)
Down counter (7 bits)
Down counter (7 bits)
CDIVR2(7 bits)
Down counter (6 bits)
CDVC
CPS1,
CPS0
CTMR(6 bits)
W
W
Figure 26.65 CFG Frequency Divider
Internal bus
UDF
UDF
S
CMK
R
CDVC
UDF
W R
Internal bus
R/W W
CDVC CDVC
MCGin CMN
φs = fosc/2
DVCFG
DVCFG2