Timer J Status Register (Tmjs) - Hitachi H8S/2199 Hardware Manual

13.2.3

Timer J Status Register (TMJS)

Bit :
Initial value :
R/W :
Note: * Only 0 can be written to clear the flag.
The timer J status register (TMJS) works to indicate issuance of the interrupt request of timer J.
The TMJS is an 8-bit read/write register. When reset, the TMJS is initialized to H'3F.
Bit 7    TMJ2I Interrupt Requesting Flag (TMJ2I)
Bit 7
TMJ2I Description
0 [Clearing conditions]
When 0 is written after reading 1
1 [Setting conditions]
When the TMJ-2 underflows
Bit 6    TMJ1I Interrupt Requesting Flag (TMJ1I): This is the TMJ1I interrupt requesting flag.
This flag is set out when the TMJ-1 underflows.
TMJ1I interrupt requests will also be made under a 16-bit operation.
Bit 6
TMJ1I Description
0 [Clearing conditions]
When 0 is written after reading 1
1 [Setting conditions]
When the TMJ-1 underflows
Bits 5 to 0    Reserved: These bits cannot be modified and are always read as 1.
Rev. 1.0, 02/00, page 270 of 1141
7 6
TMJ2I TMJ1I
0 0
R/(W)* R/(W)*
5 4 3
— — —
1 1 1
— — —
2 1 0
— — —
1 1 1
— — —
(Initial value)
(Initial value)