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23.2.8
DDC Switch Register (DDCSWR)
Bit :
SWE
Initial value :
R/W :
R/W
Notes: 1.
Only 0 can be written to clear the flag.
2.
Always read as 1.
DDCSWR is an 8-bit read/write register that controls automatic format switching for IIC channel
0 and IIC internal latch clearing. DDCSWR is initialized to H'0F by a reset or in hardware standby
mode.
Bit 7 DDC Mode Switch Enable (SWE): Enables or disables automatic switching from
formatless transfer to I
Bit 7
SWE
Description
0
Disables automatic switching from formatless transfer to I
IIC channel 0.
1
Enables automatic switching from formatless transfer to I
channel 0.
Bit 6 DDC Mode Switch (SW): Selects formatless transfer or I
channel 0.
Bit 6
SW
Description
2
0
I
C bus format is selected for IIC channel 0.
[Clearing conditions]
1. When 0 is written by software
2. When an SCL falling edge is detected when SWE = 1
1
Formatless transfer is selected for IIC channel 0.
[Setting condition]
When 1 is written after SW = 0 is read
7
6
SW
0
0
R/W
R/W
2
C bus format transfer for IIC channel 0.
5
4
IE
IF
CLR3
0
0
R/(W)*
1
W*
3
2
CLR2
CLR1
1
1
2
W*
2
W*
2
C bus format transfer for
2
C bus format transfer for IIC
2
C bus format transfer for IIC
Rev. 1.0, 02/00, page 485 of 1141
1
0
CLR0
1
1
2
W*
2
(Initial value)
(Initial value)
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